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CS-EE 481 1Founder’s Day University of Portland School of Engineering Project Yew Inline Power Monitor with Cost Analysis Team Zubin Bagai Jon Worley Kevin.

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Presentation on theme: "CS-EE 481 1Founder’s Day University of Portland School of Engineering Project Yew Inline Power Monitor with Cost Analysis Team Zubin Bagai Jon Worley Kevin."— Presentation transcript:

1 CS-EE 481 1Founder’s Day University of Portland School of Engineering Project Yew Inline Power Monitor with Cost Analysis Team Zubin Bagai Jon Worley Kevin Eldrige Faculty Advisors Dr. Albright, Dr. Osterberg Industry Representative Mr. John Haner Bonneville Power Administration

2 CS-EE 481 2Founder’s Day University of Portland School of Engineering Agenda Introduction Jon Worley Background Kevin Eldrige Research/Design Zubin Bagai Results Jon Worley Conclusions Kevin Eldrige Demonstration Team Yew

3 CS-EE 481 3Founder’s Day University of Portland School of Engineering Introduction The Problem: –The U.S. is a top consumer of energy –The typical household uses appliances when it is convenient to do so –Lack of knowledge about which appliances use the most energy, inefficient

4 CS-EE 481 4 The Solution: –In-line Power Monitor with Cost Analysis Introduction (Cont’d) Founder’s Day University of Portland School of Engineering

5 CS-EE 481 5 The Goal: Relate W to $ -Monitor the power usage of a household appliance -Utilize a keypad and LCD to make the monitor fully interactive with the user -Provide education about device efficiency, costs associated with time-of-use -Project model: Sense  Process  Actuate Background Founder’s Day University of Portland School of Engineering

6 CS-EE 481 6Founder’s Day University of Portland School of Engineering Background (Cont’d) Power Sensing -Measurements of voltage and current -Safety in design -Use components that are low power

7 CS-EE 481 7 Background (Cont’d) Data Processing: -Analog-to-Digital signal conversion (PIC) -Needs to handle keypad input & LCD output (PIC) -MOSIS capabilities (What functions can we design?) Founder’s Day University of Portland School of Engineering

8 CS-EE 481 8Founder’s Day University of Portland School of Engineering Research Desired functionality of the project –Monitor Power –LCD display (small) –Ability to switch power on/off How do we produce this functionality Feasible? What will we be able to do with the MOSIS Result of research –Power Sensing –Data Processing –User Input

9 CS-EE 481 9Founder’s Day University of Portland School of Engineering Design Integration of all parts into a single unit

10 CS-EE 481 10 Design (Cont’d) Founder’s Day University of Portland School of Engineering Power Sensing –Measures voltage drop and current draw of device –Translates these values into small voltages ‒ Small voltages sent into Opto-Isolators

11 CS-EE 481 11 Design (Cont’d) Data Processing –PIC Calculates power, takes keypad info to calculate cost, outputs to LCD, sends power prices to the MOSIS chip –MOSIS –Determines whether the threshold price is exceeded, controls the SS relay, keeps track of time –Solid State Relay Receives signal from MOSIS to allow/block power to device Founder’s Day University of Portland School of Engineering

12 CS-EE 481 12 Design (Cont’d) Founder’s Day University of Portland School of Engineering

13 CS-EE 481 13 Results Founder’s Day University of Portland School of Engineering

14 CS-EE 481 14 Results (Cont’d) Founder’s Day B 2 Logic Schematic University of Portland School of Engineering

15 CS-EE 481 15 Results (Cont’d) Founder’s Day LEDIT Layout University of Portland School of Engineering

16 CS-EE 481 16 System Results Individual √ Power Sensing √ ADC √ Solid State Relay √ MOSIS √ LCD √ Key-Pad System √ Power Sensing √ ADC √ Solid State Relay √ MOSIS √ LCD √ Key-Pad √ Power Calculation University of Portland School of Engineering Founder’s Day

17 CS-EE 481 17 System Results Founder’s Day University of Portland School of Engineering V Line =1001* ((V V-ADC -*19.5mV) -Vref/2)*(0.512/Vref) I Line =(1/0.015)* ((V I-ADC *19.5mV) -Vref/2)*(0.512/Vref) V RMS = K V (V ADC – V Zero ) I RMS = K I (I ADC – I zero ) Power (W) = V RMS *I RMS Cost = (¢/W-M) * Power 4.23 %Error 1¢/kW-H Theoretical Calibration Calculation Result Maximum Error

18 CS-EE 481 18 Conclusion In-line Power Monitor with Cost Analysis –Goal: Educate, initiate change in energy-use habits Enhancements: –Expand power factor table –10 bit ADC –Current sensing resistor network –Auto-calibration function in PIC –Wireless/Ethernet connectivity –Software to track energy consumption Founder’s Day University of Portland School of Engineering

19 CS-EE 481 19Founder’s Day University of Portland School of Engineering Demonstration Simulation of In-line Power Monitor with Cost Analysis

20 CS-EE 481 20Founder’s Day University of Portland School of Engineering Special Thanks Dr. Robert Albright Dr. Peter Osterberg Dr. Joe Hoffbeck Dr. Wayne Lu Mr. John Haner Mr. Craig Henry Mr. Steve Westdal Grant from the MOSIS Educational Program (MEP)

21 CS-EE 481 21Founder’s Day University of Portland School of Engineering Thank You. Are there any questions?


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