1. Test and Verification Solutions121 st April 2010 Integrating Ethernet CMS with Internal Verification Environments Cadence Verification Challenge, Bristol, Mike Bartley, TVS

2. 2 10 October 2015 Test and Verification Solutions221 st April 2010 Overview Background –The DUT –The verification environments Experiences –Of integrating verification environments and results –Of OVM scoreboard Results

3. 3 10 October 2015 Test and Verification Solutions321 st April 2010 The DUT: Blocks from Gnodal Ethernet chip PCS MAC Media Access Control Sublayer Physical Coding Sublayer Data Link Layer (Layer 2) PHY Layer (Layer 1) Blocks from an Ethernet chip from Gnodal

4. 4 10 October 2015 Test and Verification Solutions421 st April 2010 Internal block level verification flow Use of PSL + IFV Test bench –SystemC (sequencers and transactors) –PSL assertions in the design –SystemC coverage and assertion checks –SV covergroups and assertions There are numerous simulator tools/languages –It makes sense to pick the right tool for each job –For example PSL/SVA and SV covergroups are great for checking internal stuff in the guts of the design, in an unobtrusive way Whilst e and SC are good for the higher-level test control… –Need to consider re-use too (Gnodal had SystemC chip test bench)

5. 5 10 October 2015 Test and Verification Solutions521 st April 2010 Description of the internal test bench PCS Loopback - Injects clock and lane skew stimulus transactor Scoreboard SystemC Verilog KEY CPU System Verilog PSL irun IFV Coverage Assertion checks Coverage Assertions

6. 6 10 October 2015 Test and Verification Solutions621 st April 2010 Description of the internal test bench MAC SystemC Verilog KEY CPU Scoreboard stimulus transactor stimulus transactor PSL Coverage Assertions System Verilog PSL irun IFV Coverage Assertion checks

7. 7 10 October 2015 Test and Verification Solutions721 st April 2010 Description of the CMS test bench eVC incl coverage & assertions SystemC Verilog KEY OVM e Scoreboard e PCS MAC Loopback - Flow control CPU System Verilog Coverage Assertions irun Coverage Assertion checks

8. 8 10 October 2015 Test and Verification Solutions821 st April 2010 Experiences of using the Ethernet eVC/CMS Connecting the eVC –Quick and easy Extensive assertions related to IEEE specification Extensive coverage targets related to IEEE spec –Comprehensive and easy to adapt to our needs (using VManager) Tests –Obtained reasonably good coverage out of the box –Easy to add additional tests Injecting errors where we wanted –Layered approach – but we could only see how to inject errors after packet construction –This made it hard to cover all the state machines which required error injection at specific times/ in specific sequences

9. 9 10 October 2015 Test and Verification Solutions921 st April 2010 OVM e scoreboard : I nstance and connect 1.Define new scoreboard type and declare its ports unit vr_enet_scbd like ovm_scoreboard { scbd_port in_packet: add vr_enet_packet; scbd_port out_packet: match vr_enet_packet; }; 2.Connect it to the environment monitor/s extend vr_enet_env { scbd : ACTIVE vr_enet_scbd is instance; connect_ports() is also { do_bind ….. } };

10. 10 10 October 2015 Test and Verification Solutions1021 st April 2010 OVM scoreboard : Add and match 3.Customize the packet add and match criteria unit vr_enet_scbd like ovm_scoreboard { in_packet_predict (pkt : vr_enet_packet) is only { -- Add as UNCERTAIN; }; out_packet_reconstruct (pkt : vr_enet_packet) is only { -- Perform checks, match in scoreboard }; extend vr_enet_env { // add tcm to monitor inputs and update packet status // from UNCERTAIN to PENDING if appropriate };

11. 11 10 October 2015 Test and Verification Solutions1121 st April 2010 Experiences of using the OVM e scoreboard Easy to import and adapt Predicting which packets get dropped is hard –Ethernet can silently drop packets! –Difficult to align with packet boundaries from eVC –The DUT has windows of time for errors We may or may not lose the link We therefore slackened off the scoreboard –With the risk of missing errors

12. 12 10 October 2015 Test and Verification Solutions1221 st April 2010 Integrating verification environments in VManager Apply internal perspective Internal vsif file CMS vsif file Merge vsif files Target vsif file

13. 13 10 October 2015 Test and Verification Solutions1321 st April 2010 Integrating verification results using VManager Internal vsof files CMS vsof files Merge Single vsof file

14. 14 10 October 2015 Test and Verification Solutions1421 st April 2010 Results CvgeState ment Expre ssion ToggleCMS functional Gnodal functional CMS88%73%40%92%28% Gnodal100%95%91%NA76% Combined100%95%91%92%76% SetupRun testsAdd checks Review coverage and add tests Signoff coverage holes Effort25%5%35%25%10% Time10%40%15%30%5% Mutation –The designer inserted a number of bugs in the design –The test bench found them all Coverage low because MAC in static cfg Coverage low because did not merge in MAC cvge

15. 15 10 October 2015 Test and Verification Solutions1521 st April 2010 Conclusions The eVC was easy to install and connect Comprehensive assertions related to IEEE spec The CMS functional coverage targets –Comprehensive and easy to adapt for our perspective –Easy to integrate with our coverage targets (VManager) The CMS tests –good coverage and were easy to extend Ethernet scoreboarding is hard to predict Easy to merge CMS and internal coverage –Merge functional and code coverage