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February 28 – March 3, 2011 Stepwise Refinement and Reuse: The Key to ESL Ashok B. Mehta Senior Manager (DTP/SJDMP) TSMC Technology, Inc. Mark Glasser.

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Presentation on theme: "February 28 – March 3, 2011 Stepwise Refinement and Reuse: The Key to ESL Ashok B. Mehta Senior Manager (DTP/SJDMP) TSMC Technology, Inc. Mark Glasser."— Presentation transcript:

1 February 28 – March 3, 2011 Stepwise Refinement and Reuse: The Key to ESL Ashok B. Mehta Senior Manager (DTP/SJDMP) TSMC Technology, Inc. Mark Glasser Verification Technologist Mentor Graphics Shabtay Matalon ESL Market Development Manager Mentor Graphics Dan Gardner Technical Marketing Engineer Mentor Graphics

2 Trends … 15 billion connected devices by 2015 Basic + Smart + Enhanced phones = 2 billion phones by 2012 Mobile processor clock speed > 1 GHz (32 nm HKMG) Smart phone > 200 million triangles/sec by 2011 Highly integrated devices with audio, video, 3D graphics, text connected to Internet; require long battery life Marvell’s ARMADA 628 SoC –1.5 GHz tri-core processor –dual stream 1080p 3D video –3D graphics performance with 200 million triangles per second –for ultra-low-power, long battery life smartphones and tablets 2 of 19

3 Trends … Rapid proliferation of MP-SoC with multiple concurrent software applications Source: Next Generation Embedded Hardware Architecture - VDC of 19

4 It’s a struggle … Source: The International Technology Roadmap for Semiconductors (ITRS), 2008 Update) Cost of design tasks per technology Power requirement vs. power trends It’s a development struggle It’s a power struggle 4 of 19

5 Current Reality … Source : Semiconductor Industry Association. International Technology Roadmap for Semiconductors Chip complexity versus design productivity 5 of 19

6 Transaction-level models (TLM) allow designers to: –Build platforms for software development and hardware architecture exploration before committing to RTL –Manage the complexity of sophisticated large-scale SoCs –Build and verify SoCs more quickly –Run simulations orders of magnitude faster than RTL Reuse TLM as RTL verification testbench component Standards-driven: OSCI TLM, SystemC, C++, OVM, SystemVerilog ESL Verification Flow – Why? 6 of 19

7 ESL Verification Flow Benefits Demonstrates verification methodology early in the design before RTL is created or synthesized –Designers can validate their design specification at the TLM –Verification engineers can reduce RTL verification effort by starting validation at the TLM Common design and testbench throughout the flow, from C++/SystemC to RTL –Design block and stimulus reuse 7 of 19

8 TSMC REFERENCE FLOW 11 MENTOR SOLUTION (release on TSMC-online) 8 of 19

9 Design Example – IDCT + AXI Inverse Discrete Cosine Transform (IDCT) – design block used in JPEG/MPEG Design example connects IDCT to AXI bus (slave) IDCT IDCT_HIDCT_V REGFILE PP1 REGFILE PP0 11-bit signed 8-bit signed AXI Bus AXI Slave 9 of 19

10 C++ IDCT Model Stage 1: Algorithmic Model represented in pure C++ Verified using C++ testbench 10 of 19 C++ Stimulus Generator User-created

11 Stage 2: Transaction Level Model Algorithmic models transformed to SystemC transaction-level models –TLM2.0 for interface protocol –Timing/Power policies added TLM assembled to create the transaction-level platform SystemC model 11 of 19 SystemC/TLM2.0 provides standard interfaces for communication between models C++ Stimulus Generator C++ IDCT Model User-created (from Stage1) User-created (from Stage1) Vista Model Builder IDCT TLM Stimulus Generator TLM C++ Stimulus Generator C++ IDCT Model Vista Model Builder TP

12 Stage 2: Transaction-Level Validation, Debug, and Coverage Vista simulation and debug are used to validate results –Transaction View –SystemC Process View Coverage collector TLM determines if TLM DUT sufficiently exercised Coverage Collector TLM Validate & Debug in TLM Domain Vista IDCT TLM Stimulus Generator TLM C++ Stimulus Generator C++ IDCT Model 12 of 19

13 Stage 2: Preparing for Reuse in OVM TLM1  TLM2 translator added TLM DUT verified in a TLM1.0 configuration on Vista or Questa IDCT TLM is now ready for reuse as a reference model in OVM 13 of 19 TLM2.0 wrapper IDCT TLM TLM1  TLM2 translator IDCT TLM C++ IDCT Model Stimulus Generator TLM Stimulus Generator TLM C++ Stimulus Function TLM1.0 wrapper C++ Stimulus Generator Vista or Questa

14 Stage 3: High Level Synthesis and Verification Starting point of the design is fixed-point C++ or SystemC User-created C++ testbench is reused throughout the flow Catapult synthesizes C++ design to RTL and creates transactors Transactors convert function calls to pin-level signal activity and vice versa Comparator compares RTL DUT output against the C++ model output 14 of 19 Comparator Golden resultsDUT results C++ Stimulus Generator User-created testbench C++ IDCT Model User- created IDCT design block SCVerify automated verification flow Driver IDCT RTL Block Monitor Catapult

15 Stage 3: OVM Block Testbench IDCT agent drives the DUT –Sequence Interface: Host to sequences –Analysis Port: makes available the transactions to components outside the agent –Virtual Interface: interface object that contains the pins that are on the DUT Other elements –Sequences: behaviors that generate stimulus for DUT –Scoreboard: determines if DUT provides correct response for a given stimulus 15 of 19

16 Stage 4: Bus Integration 16 of 19 From Stage 2 From Stage 3 IDCT Agent in passive mode (active monitor but in-active driver) Adds AXI interface to Stage 3 Reusing IDCT TLM + IDCT agent Demonstrates whitebox coverage

17 Stage 5: System-Level Step Adds AXI Switch Enables reuse in a complete system 17 of 19

18 The ESL Verification Demo Kit in TSMC RF11 Shows: Verification of C++ IDCT model Construction of TLM from C++ models Transaction-level assembly, validation, and debug Validation of synthesized IDCT block against original untimed C++ model using SCVerify flow Cross-probe synthesized RTL from original C++ and vice-versa Reuse of IDCT TLM and C++ stimulus in OVM RTL block-level verification Reuse of IDCT TLM in OVM RTL block-level verification of the IDCT with AXI slave adapter 18 of 19

19 Benefits to the Verification Engineer Early and faster design validation using TLM before RTL Design and stimulus reuse throughout the flow from C++/SystemC to RTL –No need to maintain different models Verification early in the design phase before RTL is created or synthesized 19 of 19 Mentor ESL Verification Flow Kit for TSMC RF11 is released on TSMC-online


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