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Introduction to Programmable Logic Devices John Coughlan RAL Technology Department Electronics Division.

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1 Introduction to Programmable Logic Devices John Coughlan RAL Technology Department Electronics Division

2 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Lecture Outline n Programmable Logic Devices u Basics u Evolution n Field Programmable Gate Arrays (FPGAs) u Architecture n Design Flow u Design Tools u Hardware Description Languages n Industry Trends

3 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Digital Logic Connect Standard Logic Chips Very Simple Glue Logic Black Box SUM of PRODUCTS FIXED Logic Truth Table Boolean Logic Minimisation Transistor Switches Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)

4 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Programmable Logic Devices PLDs Sum of Products Un-programmed State n Different Types n SUM of PRODUCTS n Prefabricated n Programmble Links n Reconfigurable Logic Function Programmed PLD Product Terms Sums Planes of ANDs, ORs ANDs OR Inputs

5 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Complex PLDs n CPLDs n Programmable PLD Blocks n Programmable Interconnects n Electrically Erasable links CPLD Architecture Feedback Outputs

6 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Application Specific Integrated Circuits ASICs Large Complex Functions. Millions of Gates Customised for Extremes of Speed, Low Power, Radiation Hard (Very) Expensive (in small quantities) > $1 Million mask set (Very) Hard to Design. Long Design cycles. NOT Reprogrammable. High Risk Limited Complexity Thousands of Gates Cheap Easy to Design Reprogrammable. Custom Fabricated Design from Scratch Prefabricated Programmed

7 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Application Specific Integrated Circuits ASICs Large Complex Functions Inexpensive Easy to Design Reprogrammable. FPGA

8 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Field Programmable Gate Arrays FPGA n Field Programmable Gate Array u New Architecture u ‘Simple’ Programmable Logic Blocks u Massive Fabric of Programmable Interconnects Large Number of Logic Block ‘Islands’ 1,000 … 100,000+ in a ‘Sea’ of Interconnects FPGA Architecture

9 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Logic Blocks n Logic Functions implemented in Lookup Table LUTs n Multiplexers (select 1 of N inputs) n Flip-Flops. Registers. Clocked Storage elements. FPGA Fabric Logic Block (Block Cell)

10 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Lookup Tables LUTs n LUT contains Memory Cells to implement small logic functions n Each cell holds ‘0’ or ‘1’. n Programmed with outputs of Truth Table n Inputs select content of one of the cells as output 3 Inputs LUT -> 8 Memory Cells Static Random Access Memory SRAM cells 3 – 6 Inputs Multiplexer MUX

11 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Logic Blocks n Larger Logic Functions built up by connecting many Logic Blocks together

12 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Clocked Logic n Flip Flops on outputs. CLOCKED storage elements. n Sequential Logic Functions (cf Combinational Logic LUTs) n Pipelines. Synchronous Logic Design n FPGA Fabric driven by Global Clock (e.g. BX frequency) FPGA Fabric Clock

13 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk FPGA Design Synchronous Logic n Pipelining Logic n Combinational Logic Result

14 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk FPGA Design Synchronous Logic n Pipelining Logic n Combinational Logic Stored in Registers. n Clocked Logic (e.g. at LHC BX 40 MHz) Once Pipeline Full New Result every Clock Period

15 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk FPGA Design Synchronous Logic n Pipelining n Combinational and Sequential Logic. n Clocked Logic (e.g. at LHC BX 40 MHz)

16 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Clocked Logic n FPGA Fabric driven by Global Clock (e.g. BX frequency) FPGA Fabric Clock Register Transfer Logic RTL

17 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Routing n Connections Routing signals between Logic Blocks n Determined by SRAM cells Around Fabric Edges Configurable Input Output I/O Blocks 100’s – 1,000 Pins Special Routing for Clocks

18 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Configuring an FPGA n Millions of SRAM cells holding LUTs and Interconnect Routing n Volatile Memory. Loses configuration when board power is turned off. n Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. ROM or Digital Camera card n Configuration takes ~ secs JTAG Testing JTAG Port Programming Bit File

19 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Designing Logic with FPGAs n High level Description of Logic Design u Hardware Description Language (Textual) n Compile (Synthesise) into Netlist. n Boolean Logic Gates. n Target FPGA Fabric u Mapping u Routing n Bit File for FPGA n Commercial CAE Tools (Complex & Expensive) n Logic Simulation Design Flow

20 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Hardware Description Languages n High Level Description of Logic u Program Statements. Loops. If Statements …etc n Describing Mixture of Combinational and Sequential (Clocked) Logic and Signals between. n Register Transfer Level Description n Program Describes how to construct Hardware logic. n Unlike conventional Programming Language generating machine code for Sequential Processor n In practice often closely tied to Hardware (like Assembly Language) u Non Portable n Electronics Engineers call code “Firmware” n VHDL (VHSIC Hardware Description Language) u Very High Speed Integrated Circuit n VERILOG Language

21 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk architecture Behavioral of dpmbufctrl is signal acount : std_logic_vector(31 downto 0); signal dcount : std_logic_vector(31 downto 0); signal bram_addr_i : std_logic_vector(31 downto 0); begin bram_en <='1'; bram_rst <= '0'; --bit order reverse address and data buses to match EDK scheme bram_addr(0 to 31) <= bram_addr_i(31 downto 0); --N.B. EDK DOCM addresses are byte orientated count in 4s for whole words g1 : process(clk, rst) variable state : integer range 0 to 3; variable buf_zone: integer range 0 to 1; begin if clk'event and clk = '1' then if rst = '1' then buf_zone:=0; acount '0'); dcount '0'); bram_wen '0'); bram_addr_i <= X"00001FFC"; -- bram_dout_i '0'); state:=0; elsif state = 0 then --wait for din(0) at address 1FFC to be set to zero --what about pipeline of BRAM - need to wait before polling? bram_wen '0'); acount '0'); bram_addr_i <= X"00001FFC"; bram_dout_i '0'); dcount <= dcount; if bram_din_i = X"00000000" then state := 1; else state := 0; end if; VHDL Firmware Signals Parallel Processes Flip Flop Registers If Else Blocks Variables Signal Assignments Architecture Cf High Level Software Language C, Pascal Code Blocks Functions Multiplexers

22 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Field Programmable Gate Arrays FPGA n Large Complex Functions n Programmability, Flexibility. n Massively Parallel Architecture n Processing many channels simultaneously cf MicroProcessor sequential processing n Fast Turnaround Designs n SRAM Based. Standard IC Manufacturing Processes (Memory Chips) n Leading Edge of Moore’s Law n Mass produced. Inexpensive. n Many variants. Sizes. Features. n Not Radiation Hard n Power Hungry

23 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Trends n State of Art is 65nm on 300 mm wafers n Top of range 100,000+ Logic Blocks n 1,000 pins (Fine Pitched Ball Grid Arrays) n Logic Block cost ~ 1$ in 1990 ; $0.002 in 2005 n Challenges u Power. Leakage currents. u Signal Integrity u Design Gap F CAE Tools

24 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Summary n Programmable Logic Devices u Basics u Evolution n Field Programmable Gate Arrays (FPGAs) u Architecture n Design Flow u Hardware Description Languages u Design Tools n Trends n Importance for Particle Physics Experiments

25 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) john.coughlan@rl.ac.uk Highly Recommended Books n Bebop to the Boolean Algebra n Clive Maxfield n Published by Newnes n The Design Warrior’s Guide to FPGAs n Clive Maxfield n Published by Newnes n Fundamentals of Digital Logic with VHDL n Stephen Brown, Zvonko Vranesic n Published by McGraw Hill

26 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) FPGA Brands n Xilinx n Altera n Lattice Semiconductor n Microsemi (was Actel) n QuickLogic john.coughlan@rl.ac.uk

27 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) xilinx john.coughlan@rl.ac.uk

28 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Altera john.coughlan@rl.ac.uk

29 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Altera john.coughlan@rl.ac.uk

30 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) microsemi

31 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) microsemi john.coughlan@rl.ac.uk

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