1. Low Cost FPGAs March 2006

2. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 2 Breakthrough!  Low Cost, LUT-based FPGA –6K to 70K LUT4s –12K to 136K bits distributed memory –95 to 628 I/O –High volume prices as low as $0.50 per 1K LUTs  Flexible sysIO TM Buffers –LVCMOS 33/25/18/15/12, PCI –SSTL3/2/18 & HSTL15 & HSTL18 –Bus-LVDS, MLVDS, LVPECL & LVDS  Pre-engineered Source Synchronous I/Os –DDR2 (400Mbps)  sysDSP TM High Performance DSP Support –12 to 88 18x18 multipliers  sysMEM TM Block Memory –55K to 1M bits  sysCLOCK TM PLL and DLL  Enhanced Configuration Support –Configuration bitstream encryption –Transparent updates –Dual boot support LatticeECP2 – Low Cost & High Performance Low Cost 840Mbps Parallel I/O 28 GMAC DSP Bitstream Encryption 400Mbps DDR2

3. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 3 Breakthrough! LatticeECP2 – Architecture Configuration Port Programmable Function Units (PFUs) Flexible sysIO Buffers: LVCMOS, HSTL,SSTL, LVDS, ++ DSP Blocks Multiply and Accumulate Support sysMEM Block RAM 18kbit Dual Port sysCLOCK PLLs & DLLs Frequency Synthesis & Clock Alignment Config. Logic Inc Dual Boot, Encryption & Transparent Updates Flexible Routing Optimized for Speed, Cost and Routability Pre-Engineered Source Synchronous Support DDR2 – 400Mbps Generic – 840Mbps On-Chip Oscillator

4. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 4 Breakthrough! Optimized Programmable Function Unit (PFU)  PFU Resources Optimized –Best match to applications –Best speed –Best cost  Tools Tuned To Optimally Use Available Resources SLICE 0 LUT4 FF SLICE 1 LUT4 FF SLICE 2 LUT4 FF From Routing To Routing SLICE 3 LUT4 Carry Chain Logic Block (PFU) LUT4ROMCarryFFRAM 1 Slice 0 Slice 1 Slice 2 Slice 3 1. Available in 25% of the PFUs

5. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 5 Breakthrough! Extensive High Performance Clocking  High Performance Clock Distribution –Eight global clock networks –Eight regional secondary clocks –Two low-skew edge clocks per side  sysCLOCK PLL and DLL Technology –2 to 6 PLLs per device »External capacitor allows operation as low as 1MHz »Dynamic phase shift capability –2 DLLs per device »Includes slave delay for source synchronous implementations  On-Chip Oscillator (Typ 130MHz)  Edge Clock Divider –X2, X4, X8 –For high speed source synchronous implementations

6. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 6 Breakthrough! sysCLOCK PLL  Two General Purpose PLLs (GPLLs) Per Device  Up To Four Standard PLLs (SPLLs) Per Device  Frequency Range 1 to 420MHz  Programmable Phase / Duty Cycle (22.5 degree steps)  Programmable Dividers  Internal and External Feedback  PLLs Filter Jitter Feedback Divider (CLKFB) PLL Post Scalar Divider (CLKOP) Input Clock Divider (CLKI) Phase & Duty Select Secondary Clock Divider (CLKOK) Adjust* Delay CLOCK IN (From pin or routing) CLOCK OUT LOCK CLOCK OUT Dynamic Adjust Feedback (From post scalar divider, clock net or external pin) Dynamic Adjust Optional External Capacitor * GPLL Only +/- 8 Steps 130ps Nominal

7. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 7 Breakthrough! sysCLOCK DLL  Flexible DLL Provides 3 Modes: –Calibrated delay –Clock injection removal –Clock match  100 to 500MHz Operation  DLLs Maintain Clock and Data Alignments Phase Comparator Clock In (From pin or routing ) Clock Out Lock Feedback (DLL Internal, clock net or external pin) ALU Delay Line 50% Duty Cycle 50% Duty Cycle  2/4 Clock In (From pin or routing ) Output Mux Clock Out sysCLOCK DLL Matched Delay Delay Line Clock Out Note: Simplified diagram

8. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 8 Breakthrough! On-Chip Oscillator  On-Chip Oscillator Provides Low Cost Clock –Ideal for non-timing-critical state machines  Drives Internal Routing –Can be routed off chip  Nominal Frequency Can Be Set 2.5 to 130Mhz  Easily Implemented With ispLEVER Design Tools COMPONENT OSCD -- synthesis translate_off GENERIC(NOM_FREQ: string := 2.5); -- synthesis translate_on PORT (OSC:OUT std_logic); END COMPONENT; attribute NOM_FREQ : string; attribute NOM_FREQ of OSCins0: signal is “2.5”; OSCD OSC Oscillator Primitive Example VHDL Usage

9. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 9 Breakthrough! High-Performance sysDSP Block  Programmable Multiplier –One 36x36 or four 18x18 or eight 9x9  Programmable Addition, Subtraction & Accumulate  Programmable Pipelining –Input / Intermediate / Output  325MHz Performance –Provides up to 28.6 GMAC/second per device  Suitable For Wide Range of DSP Functions Including –FIR Filters, FFTs and complex arithmetic X X +-  X X + + sysDSP Block

10. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 10 Breakthrough! DQS/Strobe Delay and Transition Detect* PIO A Tri-state Register Block (2 Flip/flops) Input PIC Pre-Engineered Source Synchronous I/O  Implement High Speed Memory Interfaces –DDR1/2  Implement High Speed Source Synchronous Interfaces –SPI4.2 –ADC/DAC  Pre-Engineered I/O Logic Support –DDR to SDR conversion –Gearbox logic –DQS/Strobe alignment DDR to SDR Conversion Output Register Block (2 Flip/flops) Input Register Block (5 Flip/flops) PIO B (Detail Not Shown) * Selected blocks 2:1 Gearbox (Optional) Shared With PIO B Precision Strobe/DQS Alignment 2:1 Gearbox For Operation Up to 840Mbps

11. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 11 Breakthrough! sysIO Support * Includes PCI clamping diode. Bottom I/Os only ** HSTL II outputs only supported for 1.8-volts *** Drivers on 50% of pairs left and right side of the device only **** LVPECL and BLVDS can be supported through emulation StandardClock Speed LVTTL, LVCMOS 3.3/2.5/1.8/1.5/1.2 V 166MHz333Mbps PCI* 66MHz SSTL 18/2/3 (I, II)200MHz400Mbps HSTL 18/15 (I, II**)200MHz400Mbps LVDS***420MHz840Mbps Differential HSTL200MHz400Mbps Differential SSTL200MHz400Mbps sysIO Buffer SupportChip Level Support StandardSpeed DDR1/2 Memory400Mbps PCI 66MHz Generic Source Synch.840Mbps

12. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 12 Breakthrough! LVCMOS/LVTTL I/O Features  Hotsocketing Capable –Input leakage less than 1mA during power-up/power-down –Power supplies can be sequenced in any order  Programmable Slew Rate  Programmable Drive Strength –4 to 20mA (3.3-volts) –4 to 20mA (2.5-volts) –4 to 16mA (1.8-volts) –4 to 8mA (1.5-volts) –2 to 6mA (1.2-volts)  Programmable Pull-up, Pull-down, Bus-friendly  Programmable Open Drain

13. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 13 Breakthrough! I/O Banking Scheme  Eight General Purpose I/O Banks Per Device –Configuration pins in separate bank  Output Standard Support Dependent on V CCIO  Referenced Inputs Dependent on V REF  LVCMOS Inputs –12, 25 & 33 independent of V CCIO –15 & 18 dependent on V CCIO  Multiple Compatible I/O Standards In A Bank V REF1(2) GND Bank 2 V CCIO2 V REF2(2) V REF1(3) GND Bank 3 V CCIO3 V REF2(3) V REF1(7) GND Bank 7 V CCIO7 V REF2(7) V REF1(6) GND Bank 6 V CCIO6 V REF2(6) V REF1(5) GND Bank 5 V CCIO5 V REF2(5) V REF1(4) GND Bank 4 V CCIO4 V REF2(4) V REF1(0) GND Bank 0 V CCIO0 V REF2(0) V REF1(1) GND Bank 1 V CCIO1 V REF2(1) GND V CCIO8 Bank 8

14. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 14 Breakthrough! Soft Error Detect (SED) Logic  LatticeECP2 Devices Contain Hard SED Logic –Not available in Spartan/Cyclone  Checks Configuration Bits In Background –Compares to CRC –Ignores EBR and distributed memory  In Case of Error Optionally: –Generates an error flag –Background reconfigures logic –Initiates a full reconfiguration  Target This Feature for High Reliability Applications –SED is a “non-issue” for most applications Configuration Logic Configuration Bits Hard SED Logic LatticeECP2

15. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 15 Breakthrough! Encryption  Design Security Increasingly Important –Overbuilding, reverse engineering and cloning all too common  Encrypt Bitstreams With 128-bit AES Using ispVM  On-Chip OTP 128-bit Decryption Key Storage –Choose your own unique key  On-Chip 128-bit AES Decryption Engine Configuration Memory 128-bit AES Encrypted Bitstream LatticeECP2 Decryption Engine 128-bit Key 128-bit Key In OTP Non-Volatile Memory Decrypted Data Configures FPGA

16. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 16 Breakthrough! Dual Boot Mode  Store Active and Backup (Golden) Configurations In SPI Configuration Memory  LatticeECP2 Will Automatically Use Golden Configuration If Active Configuration is Invalid  Increase System Reliability When Configurations are Field Updated Sector 0 Sector 1 Read Data Control LatticeECP2 LatticeECP2 Loads Active Configuration (B) at Power Up. If This Fails Configuration A is Used SPI Configuration Memory Golden (A) Configuration Active (B) Configuration

17. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 17 Breakthrough! TransFR I/O For Live Field Updates Field Update FPGAs and Maintain High System Uptime Config. 1 LatticeECP2 (Config. 2) Config. Memory Step 1 Load New Config. To Configuration Memory Step 2 Lock The I/Os In The Desired State Config. 1 LatticeECP2 (Config. 2) Config. Memory Step 3 Apply New Configuration Config.2 LatticeECP2 (Config. 2) Config. Memory Step 4 FPGA Regains Control of I/O Config.2 LatticeECP2 (Config. 2) Config. Memory

18. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 18 Breakthrough! Support Designs Over 300MHz ElementPerformance (MHz) PFU375MHz* sysCLOCK PLL Input Range 1 – 420MHz Global Clock500MHz sysMEM EBR350MHz sysDSP Block325MHz sysIO Buffer 400Mbps (DDR1/2 memory) 840Mbps (Generic Source Synch.) * Simple functions (For example 16-bit decoder, 16-bit counter)

19. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 19 Breakthrough! Device ECP2 6ECP2 12ECP2 20ECP2 35ECP2 50ECP2 70 LUTs (K)6.01221324868 sysMEM Blocks31215182156 sysMEM (Kbits)552212763313871,032 Distributed RAM (Kbits)1224426596136 # 18x18 Multipliers122428327288 PLLs/DLLs2/2 4/26/2 Package & IO Combinations 144-pin TQFP (20x20mm)95 208-pin PQFP (28x28mm)127 256-ball fpBGA (17x17mm)192 484-ball fpBGA (23x23mm)297332 339 672-ball fpBGA (27x27mm)363452500 900-ball fpBGA (31x31mm)628 SamplesQ4Q2Q3 Q1Q4 LatticeECP2 Family

20. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 20 Breakthrough! Device ECP2M 20ECP2M 35ECP2M 50ECP2M 70ECP2M 100 LUTs (K)1934486795 sysMEM Blocks5498201222264 sysMEM (Kbits)9951,8063,7054,0924,866 Distributed RAM (Kbits)4171101145202 # 18x18 Multipliers24328896168 PLLs/DLLs8/2 Package & IO Combinations 256-ball fpBGA (17x17mm)163 484-ball fpBGA (23x23mm)301 287 672-ball fpBGA (27x27mm)402387 900-ball fpBGA (31x31mm)455449457 1156-ball fpBGA (31x31mm)601 SamplesTBDQ2TBD LatticeECP2M Family

21. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 21 Breakthrough! ECP2 Timeline  Family Publicly Announced, Collateral Available Now  Limited ECP2-50 Prototypes Available Now –Broad sample availability during Q2 –Whole family planned for production by the end of 2006  Pricing As Low As $0.50 Per KLUT –Lowest speed grade, highest volume  ECP2-50 Supported in ispLEVER 5.1 SP2  Extensive IP Support Planned For 2006

22. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 22 Breakthrough! Advanced Configuration Support  Flexible Configuration Options –Low cost SPI boot memory, microprocessor, JTAG  Encrypted Bit Stream –On-chip 128-bit AES decryption –Encryption key securely stored on-chip  Automatic SPI Dual Boot –Allows recovery if power or communication fails during field update  Simple Field Configuration –Define I/O state during field configuration –Reconfigure FPGA while system operates

23. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 23 Breakthrough! ECP2 Compared to ECP FeatureECPECP2Impact Logic8 LUTs/PFU 8 Registers/PFU 25% Dist. Memory 8 LUTs/PFU 6 Registers/PFU 12.5% Dist. Memory Lower Cost Clocks4 Primary 4 Secondary 8 Primary 8 Regional 2 Edge/side Higher Speed Clocking PLLs2 – 4 25MHz – 420MHz 2 – 6 1MHz – 420MHz Flexibility DLLs02Flexibility Memory9Kb EBRs18Kb EBRsLower Cost I/OsysIO Buffer DDR Mux DQS Alignment sysIO Buffer (inc DDR2) DDR Mux + Gearbox DQS Alignment Generic DDR Higher Speed I/O Config.SPI PROMSPI PROM Dual boot Encryption Improved Configuration

24. Copyright © Lattice Semiconductor 2006 S1 Low-Cost FPGAs - February/March, 2006 – Page 24 Breakthrough! LatticeECP2 Competitive Comparison FeatureSpartan3ECyclone IILatticeECP2 DSPBasic 18x18 Multiplier Full-Featured sysDSP Block DDR / Source Synch 333Mbps DDR2 DDR Registers 333Mbps DDR2 DQS Alignment 400Mbps DDR2 DQS Alignment DDR Registers Clock Transfer Gearbox Logic Config.SPI PROMProprietary PROMSPI PROM Encryption Dual-boot TransFR Distributed Memory 50% - InefficientNoneOptimized 12.5% LogicLUT4 + Register Optimized 75% LUT4+FF 25% LUT Exceptional Performance Uncommon Value