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Technical Seminar Tour 2006 - Page 1 MachXO / XP / Overview Technical Seminar Tour 2007 LATTICES PROGRAMMABLE LOWCOST SOLUTIONS Welcome to.

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Presentation on theme: "Technical Seminar Tour 2006 - Page 1 MachXO / XP / Overview Technical Seminar Tour 2007 LATTICES PROGRAMMABLE LOWCOST SOLUTIONS Welcome to."— Presentation transcript:

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2 Technical Seminar Tour Page 1 MachXO / XP / Overview Technical Seminar Tour 2007 LATTICES PROGRAMMABLE LOWCOST SOLUTIONS Welcome to

3 Technical Seminar Tour Page 2 MachXO / XP / Overview Lattice Mach4000 TM Lattice MachXO TM Lattice MachXP TM Jörg Siemers, TMM; Avnet-Memec Non-volatile Solutions

4 Technical Seminar Tour Page 3 MachXO / XP / Overview Mach I/O Registers LatticeXP FPGA MachXO Crossover ispMACH CPLD

5 Technical Seminar Tour Page 4 MachXO / XP / Overview ispMACH 4000 Family Overview SuperFAST CPLD Family 400 MHz f MAX and 2.5ns t PD for high- system performance Low Static Power Full CMOS design with static power as low as 40 W (Z-type) Low Dynamic Power 1.8V core for low dynamic power consumption Flexible Architecture Get designs to market fast Flexible Solution - 32 to 512 macrocells - 3.3V, 2.5V or 1.8V supply - Commercial/Industrial/Automotive

6 Technical Seminar Tour Page 5 MachXO / XP / Overview Zero Power Flexible Architecture SuperFAST Performance ispMACH Optimal CPLD Solutions Mainstream CPLDs 1.8/2.5/3.3V Power Supply 1.8/2.5/3.3/5V I/O 32 to 512 Macrocells Commercial/Industrial/ Automotive Density (Macrocells) f MAX (MHz) Competition B Lattice Competition A LatticeLeadershipLatticeLeadership ORP Generic Logic Block I/O Block Generic Logic Block ORP I/O Block ORP Generic Logic Block I/O Block Generic Logic Block ORP I/O Block Global Routing Pool (GRP) BANK 0 BANK 1

7 Technical Seminar Tour Page 6 MachXO / XP / Overview ispMACH 4000 Family Supports 1.8, 2.5, or 3.3V Power Supply

8 Technical Seminar Tour Page 7 MachXO / XP / Overview ispMACH 4000 Automotive Applications Operation –40 O C to 125 O C Highest Performance Design Flexibility Lowest Power Consumption 1.8, 2.5 and 3.3V I/O (with 5V Tolerance) 4000 Automotive Features

9 Technical Seminar Tour Page 8 MachXO / XP / Overview ispMACH 4000V Automotive Family Macrocells f MAX (MHz) t PD (ns) t CO (ns) t S (ns) I/O Packages /32 44 TQFP 48 TQFP /92/ TQFP 128 TQFP 144 TQFP /96/ TQFP 144 TQFP 176 TQFP / 32/64 44 TQFP 48 TQFP 100 TQFP 4128V 4064V 4256V 4032V

10 Technical Seminar Tour Page 9 MachXO / XP / Overview ispMACH 4000Z Automotive Family Macrocells f MAX (MHz) t PD (ns) t CO (ns) t S (ns) I/O Packages TQFP / TQFP /64 48 TQFP 100 TQFP 4128Z 4064Z 4032Z / TQFP 176 TQFP 4256Z

11 Technical Seminar Tour Page 10 MachXO / XP / Overview MachXO Crossover I/O Registers LatticeXP FPGA MachXO Crossover ispMACH CPLD

12 Technical Seminar Tour Page 11 MachXO / XP / Overview MACHXO Reconfigurable Non-Volatile FLASH SRAM Bringing the Best Together FPGAs without Compromise

13 Technical Seminar Tour Page 12 MachXO / XP / Overview Fujitsu Technology Partnership Geometry Time 130nm Logic 130nm Flash + Logic Proven 130nm and 90nm Industry Leading 130nm Flash 300mm Fab for Lower Costs 65nm Development Underway 90nm Logic 65nm Logic Fujitsu & Lattice Bringing the Best Together 1.2-volt core

14 Technical Seminar Tour Page 13 MachXO / XP / Overview MachXO Brings the Best Together AttributeCPLDFPGAMachXO High Pin-to-Pin Speed Fast Wide Logic High I/O to Logic Ratio Instant-On Register Intensive Distributed & Embedded Memory MachXO Brings Together CPLD and FPGA Attributes to Optimally Serve Traditional CPLD Applications

15 Technical Seminar Tour Page 14 MachXO / XP / Overview MachXO Key Features Non-Volatile Solution –Single chip, instant-on, high security TransFR (TFR) Technology –Simplifies in-field logic updates High Performance –3.5n pin-to-pin* LUT Based Flexibility –256 to 2,280 (LUT4s) –2K to 8K bits distributed memory I/O Intensive –78 to 271 I/O Flexible sysIO TM Buffers –LVCMOS 33/25/18/15/12, LVDS**, PCI** sysMEM TM Block Memory ** –Up to 28K bits of memory sysCLOCK TM PLLs** On Board Oscillator ~20MHz 1.2/1.8/2.5/3.3V Power Supply Options –Low standby power 640 LUTs) LUT Flexibility Embedded Memory Non-volatility Performance

16 Technical Seminar Tour Page 15 MachXO / XP / Overview MachXO Block Diagram (1200 and 2280) sysMEM Block RAM 9kbit Dual Port sysCLOCK PLLs Frequency Synthesis & Clock Alignment sysIO Buffers Support LVCMOS/LVTTL, LVDS and PCI Programmable Function Units (PFUs) (with RAM) Flexible Routing Optimized for Speed, Cost and Routability Programmable Function Units (PFFs) (without RAM) JTAG Port

17 Technical Seminar Tour Page 16 MachXO / XP / Overview MachXO Block Diagram (640 and 256) Flexible Routing Optimized for Speed, Cost and Routability JTAG Port Four banks of sysIO Buffers Support LVCMOS/LVTTL Programmable Function Units (PFUs) (with RAM) Programmable Function Units (PFFs) (without RAM) MachXO 640 Two banks of sysIO Buffers Support LVCMOS/LVTTL MachXO 256

18 Technical Seminar Tour Page 17 MachXO / XP / Overview MachXO Configuration Options Flash Configures Logic, Interconnect and Block RAM for User PROMs TransFR (TFR) Technology Simplifies In-Field Logic Updates SRAM Config. Bits (Control Device Op.) FLASH MEMORY Control Logic JTAG Port Massively Parallel Wide Data Transfer ProvidesFast SRAM Configuration from FLASH Instant-on On Chip FLASH Single Chip Solution Excellent Security Infinitely Reconfigure SRAM Through JTAG Reprogram FLASH Through JTAG Port MachXO

19 Technical Seminar Tour Page 18 MachXO / XP / Overview MachXO Simplifies In-Field Logic Updates Requirement Embedded Programming Minimum Downtime I/O States Preserved Device State Controlled MachXO with TransFR (TFR) Technology ispVM Embedded Background Program Update SRAM <1mS XFLASH TransFR ispVM Command Controls I/O & Device State Transparent Field Reconfiguration (TransFR)

20 Technical Seminar Tour Page 19 MachXO / XP / Overview sysIO Interfaces sysIO Buffer Supports Multiple I/O Standards –LVTTL, LVCMOS 33/25/18/15/12 –PCI* –LVDS*, BLVDS**, LVPECL** Up to 8 I/O Banks For Flexibility in I/O Placement Hotsocketing –Input leakage less than 1mA during power-up/power-down –Power supplies can be sequenced in any order Programmable Slew Rate Programmable Drive Strength –4 to 20mA (3.3-volts) –4 to 20mA (2.5-volts) –4 to 16mA (1.8-volts) –4 to 8mA (1.5-volts) –2 to 6mA (1.2-volts) Programmable Pull-up, Pull- down, Bus-friendly Programmable Open Drain PAD TO Programmable delay element Input data signal Output data Fast output data signal GOE DO OE Output data * MachXO 1200 and 2280 ** MachXO 1200 and 2280 with external resistors

21 Technical Seminar Tour Page 20 MachXO / XP / Overview sysMEM Block RAM Configurable Width and Depth Single Port, Dual Port, Pseudo- dual Port, FIFO and ROM Modes FIFO Logic Included in EBR EBR AD[12:0] CLK CE DO[35:0] EBR AD[12:0] DI[35:0] CLK RST WE CS[2:0] DO[35:0] EBR ADA[12:0] DIA[17:0] CLKA RSTA WEA CSA[2:0] DOA[17:0] ADB[12:0] DIB[17:0] CLKB RSTB WEB CSB[2:0] DOB[17:0] EBR RAD[12:0] RD[35:0] RCE RCLK WAD[12:0] WD[35:0] WCLK WCE WE RST ROM RAM (Single Port) RAM (Dual Port) RAM (Pseudo Dual Port) Provides 9,216 Bit Blocks 275MHz Operation Efficient Implementation of Buffers Single PortDual Port Pseudo Dual Port FIFO 8,192 X 1 4,096 X 2 2,048 X X X X 36 FIFO

22 Technical Seminar Tour Page 21 MachXO / XP / Overview sysCLOCK PLL Frequency: 25MHz MHz –VCO Frequency MHz Low Output Period Jitter: ~ +-120ps Programmable Phase /Duty Cycle (45 Degree Steps) Dynamic Delay Adjust –Increments of 250ps with a total of 2ns lead or 2ns lag Divider (1-12) PLL Divider (2,4,, 24) Divider (1-12) Phase & Duty Select Adjust Delay CLOCK IN (From pin or routing) CLOCK OUT LOCK CLOCK OUT Dynamic Delay Adjust 0.25ns Steps +/- 2ns Range Feedback (From post scalar divider, clock net or external pin) Divider (2,4,,128)

23 Technical Seminar Tour Page 22 MachXO / XP / Overview Multiple Power Supply Options Use C Version to Access Latest Technology Without Adding New Power Supplies to Board –Improve performance and power consumption –Allows single supply operation from 3.3-volts Use E Version to Minimize Power Consumption –64% lower power than operation at 3.3-volts Lower Voltage (E) Version V CC V CCP V CCAUX V CCJ V CCIO 1.2 to 3.3V for Chosen I/O Std. 1.2 Volts3.3 Volts Upper Voltage (C) Version V CC V CCP V CCAUX V CCJ V CCIO 1.2 to 3.3V for Chosen I/O Std. 3.3/2.5/1.8 Volts3.3 Volts Internal logic operates at 1.2-volts MachXO

24 Technical Seminar Tour Page 23 MachXO / XP / Overview Sleep Mode Reduces Power by Factor of 1000 Mode CharacteristicNormalOffSleep SLEEPN PinHighXLow Static IccTypical <100mA0Typical <100uA Power SuppliesNormal RangeOffNormal Range Logic OperationUser DefinedNon Operational I/O OperationUser DefinedTri-State LatticeXO SLEEPN Pin Device State NormalSleep ModeNormal Typical 100nSTypical 1mS Note: Sleep Mode is only available on 1.8/2.5/3.3V C version

25 Technical Seminar Tour Page 24 MachXO / XP / Overview MachXO Benefits Self-Configuration in Under A Millisecond Instant-On ideal for system heartbeat control logic Supports configuration scrubbing for SEU control Supports rapid power cycling High Security Security bits prevent readback No exposed power-up bitstream Single Chip Simplify design Reduced PCB footprint Save boot PROM costs SRAM + FLASH TransFR (TFR) technology enables in field updates while system operates On-Chip Regulation Support legacy applications with latest technology - Reduce costs - Improve performance

26 Technical Seminar Tour Page 25 MachXO / XP / Overview MachXO Family Members DeviceLCMXO 256LCMXO 640LCMXO 1200LCMXO 2280 LUTs Distributed RAM (KBits) EBR SRAM (KBits) # EBR SRAM Blocks (9Kb) 0013 V CC Voltage Number of PLLs 0012 Max I/O Packages: 100-TQ (14X14) TQ (20X20)113 csBGA 100 (8X8)7874 csBGA 132 (8X8)101 fpBGA 256 (17X17) fpBGA 324 (19X19) /1.8/2.5/3.3V

27 Technical Seminar Tour Page 26 MachXO / XP / Overview LUTs sysMEM Blocks (9Kbits) sysMEM EBR RAM (bits) Distributed RAM (k bits) sysCLOCK PLLs Global Clocks I/O Type Pb-Free Packages / IO 100 TQFP 144 TQFP 256 ftBGA 324 ftBGA Availability (E = 1.2V) (C = 3.3/2.5/1.8V) LAMXO 256 LAMXO 1200 LAMXO 640 LAMXO LVCMOS LVCMOS 78 LA-MachXO Family LVCMOS PCI LVDS No Plan LVCMOS PCI LVDS No Plan 1 1. Due to thermal consideration.

28 Technical Seminar Tour Page 27 MachXO / XP / Overview MachXO Summary MachXO Offers a Unique Combination of Flash and SRAM Technology to Deliver Non-Volatile, In- System Reconfigurable Logic MachXO Offers an Extremely Cost-Effective Alternative to High-End CPLDs and Low-End FPGAs with the Best Features of Both Applications for MachXO Span All Market Segments and Electronic Systems The Combination of LatticeEC/ECP/XP FPGAs and MachXO Gives Lattice the Broadest Portfolio of Low-Cost FPGAs Available

29 Technical Seminar Tour Page 28 MachXO / XP / Overview XP - non volatile FPGA Family I/O Registers LatticeXP FPGA MachXO Crossover ispMACH CPLD

30 Technical Seminar Tour Page 29 MachXO / XP / Overview ispXP Reconfigurable Non-Volatile FLASH SRAM Bringing the Best Together FPGAs without Compromis e

31 Technical Seminar Tour Page 30 MachXO / XP / Overview Fujitsu Technology Partnership Geometry Time 130nm Logic 130nm Flash + Logic Proven 130nm and 90nm Industry Leading 130nm Flash 300mm Fab for Lower Costs 65nm Development Underway 90nm Logic 65nm Logic Fujitsu & Lattice Bringing the Best Together 1.2-volt core

32 Technical Seminar Tour Page 31 MachXO / XP / Overview LatticeXP FPGA Key Features Non-Volatile Reconfigurable Low Cost Solution –Optimized architecture –0.13um Flash process Wide Density & I/O Selection –3k to 20k LUTs –62 to 340 I/Os Embedded & Distributed Memory –12kbits to 79kbits distributed in LUTs –54kbits to 414kbits embedded block High Performance (225MHz+) sysIO Interface Support –LVCMOS, LVTTL, PCI, LVDS, SSTL, HSTL 333Mbps DDR Memory Interfaces sysCLOCK PLLs Two Core Power Supply Versions –C = 1.8, 2.5, 3.3V Support –E = 1.2V Support Non-Volatile Flexible LUT-Based Reconfigurable No Compromise

33 Technical Seminar Tour Page 32 MachXO / XP / Overview ispXP FLASH Memory Instant-on, Secure and Single-chip LatticeXP: Added Non-Volatility JTAG sysMEM TM Block RAM 9kbit Dual Port Optimized sysIO TM Buffers Support Mainstream I/O: LVCMOS/LVTTL, LVDS, SSTL, HSTL, DDR Memory Interfaces sysCLOCK TM PLLs Frequency Synthesis & Clock Alignment Optimized Programmable Function Units (PFUs) 25% – Logic + RAM 75% – Logic Only Flexible Routing Optimized for Speed, Cost and Routability

34 Technical Seminar Tour Page 33 MachXO / XP / Overview LatticeXP Configuration Options SRAM Configuration Bits (Control Device Operation) FLASH MEMORY Control Logic sysCONFIG Port JTAG Port Parallel sysCONFIG to Configure SRAM or Program FLASH Serial JTAG Port (IEEE 1532/1149.1) to Configure SRAM or Program FLASH On Chip Non-Volatile Single Chip Solution Excellent Security Massively Parallel Data Transfer & Multiple Blocks Provide Secure and Fast SRAM Configuration Instant-on Flash Configures Logic, Interconnect and Block RAM for User PROMs Background Flash Programming Support -Upgrade system remotely Leave-Alone I/O -Control I/O state while refreshing

35 Technical Seminar Tour Page 34 MachXO / XP / Overview Background Programming With LatticeXP Background Programming of Flash Occurs While the Device is in Normal Operation Power Cycle or Apply a Refresh Command New/Updated Configuration Takes Control Logic operates based on SRAM configuration #1 FLASH (#1 #2) FLASH Programming During Device Operation Program configuration #2 to FLASH via sysCONFIG or JTAG ports Logic operates based on SRAM configuration #2 FLASH (#2) Reload SRAM at Power-up or User Command

36 Technical Seminar Tour Page 35 MachXO / XP / Overview XP10 Programming Times SRAM Configuration –From FLASH 2ms –Via sysCONFIG 11ms –Via JTAG 100mS FLASH Programming* –Via JTAG 2 Seconds –Via sysCONFIG 2 Seconds ispXP Reconfigurable Non-Volatile * Programming time. Erase approximately 10 seconds

37 Technical Seminar Tour Page 36 MachXO / XP / Overview LatticeXP Wake-up Time LatticeXP Logic is Available 1mS After Power Good -- Supports Instant-on Application Requirements -- XP Advantage Altera Lattice EP1C12XC3S1000XP10 Wake-up Time (mS) Fastest serial configuration Xilinx

38 Technical Seminar Tour Page 37 MachXO / XP / Overview LatticeXP Integrates Multiple Components FPGA Data Path function Microprocessor CPLD Power up logic FPGA boot logic and bus decode Processor Address and Data Busses Microprocessor Processor Address and Data Busses Voltage Regulator

39 Technical Seminar Tour Page 38 MachXO / XP / Overview LatticeXP FPGAs Secure Your Design FPGA Security Important Due To Multiple Threats –Reverse engineering –Cloning –Overbuilding –Theft of service LatticeXP Security Scheme Allows Devices To Be Locked –Secures SRAM and FLASH –Erasing memory is only allowable operation –0.13um technology and 8 metal layers makes probing next to impossible Specify Secure Mode in ispLEVER or ispVM SRAM FPGAs Expose Your Intellectual Property At Power Up LatticeXP FPGAs Secure Your Design

40 Technical Seminar Tour Page 39 MachXO / XP / Overview Optimized PFU Logic Block Industry-standard 4-input LUT Structure – Combine multiple LUTs for larger functions – Carry Chain for arithmetic speed SLICE 0 LUT4 FF SLICE 1 LUT4 FF SLICE 2 LUT4 FF From Routing To Routing SLICE 3 LUT4 FF Carry Chain Logic Block (PFU) LUTs Used As Distributed Memory Frequency of Usage (>250 Designs) 0% 50% Spartan3 50% Distributed Memory Incurs Unnecessary Die Cost Cyclone 0% Distributed Memory Impacts Logic Efficiency Optimized LatticeXP Devices Support 25% Distributed Memory 10% LUTs Needed for Distributed Memory on Average Optimized Architecture Delivers Uncommon Value FF

41 Technical Seminar Tour Page 40 MachXO / XP / Overview sysMEM Block RAM Single PortDual Port Pseudo- Dual Port 8,192 X 1 4,096 X 2 2,048 X 4 1,024 X X X 36 Configurable Width and Depth Single Port, Dual Port, Pseudo- dual Port and ROM Modes Port Width Matching FIFO with surrounding logic EBR AD[12:0] CLK CE DO[35:0] EBR AD[12:0] DI[35:0] CLK RST WE CS[2:0] DO[35:0] EBR ADA[12:0] DIA[17:0] CLKA RSTA WEA CSA[2:0] DOA[17:0] ADB[12:0] DIB[17:0] CLKB RSTB WEB CSB[2:0] DOB[17:0] EBR RAD[12:0] RD[35:0] RCE RCLK WAD[12:0] WD[35:0] WCLK WCE WE RST ROM RAM (Single Port) RAM (Dual Port) RAM (Pseudo Dual Port) Provides 9,216 Bit Blocks 250MHz Operation Multiple Blocks per Device

42 Technical Seminar Tour Page 41 MachXO / XP / Overview sysCLOCK PLL Frequency Range 25 to 375MHz VCO range 420 to 750MHz Analog PLL Technology Low Output Period Jitter (+/- 125ps) Programmable Phase / Duty Cycle (45 degree steps) Programmable Dividers Internal and External Feedback Feedback Divider (CLKFB) PLL Post Scalar Divider (CLKOP) Input Clock Divider (CLKI) Phase & Duty Select Secondary Clock Divider (CLKOK) Adjust Delay CLOCK IN (From pin or routing) CLOCK OUT LOCK CLOCK OUT Dynamic Delay Adjust 0.25ns Steps +/- 2ns Range Feedback (From post scalar divider, clock net or external pin)

43 Technical Seminar Tour Page 42 MachXO / XP / Overview DQS Delay and Transition Detect* PIO A Tri-state Register Block (2 Flip/flops) Input PIC High performance sysIO Buffer (700 Mbps) 2-FF Output & Tri- state Structure Allows Easy DDR Implementation Dedicated Circuitry Simplifies DDR Memory Implementations (up to 333Mbps) 8 I/O Banks Allows Flexible I/O Implementation Output Register Block (2 Flip/flops) Input Register Block (5 Flip/flops) Control Select PIO B (Detail Not Shown) 5-Flip Flop Input Structure Allows Easy DDR Implementation (Including clock domain transfer) * Selected blocks

44 Technical Seminar Tour Page 43 MachXO / XP / Overview I/O Banking Scheme Eight I/O Banks Per Device Output Standard Support Dependent on V CCIO Referenced Inputs Dependent on V REF LVCMOS Inputs –12, 25 & 33 independent of V CCIO –15 & 18 dependent on V CCIO Multiple Compatible I/O Standards In A Bank V REF1(2) GND Bank 2 V CCIO2 V REF2(2) V REF1(3) GND Bank 3 V CCIO3 V REF2(3) V REF1(7) GND Bank 7 V CCIO7 V REF2(7) V REF1(6) GND Bank 6 V CCIO6 V REF2(6) V REF1(5) GND Bank 5 V CCIO5 V REF2(5) V REF1(4) GND Bank 4 V CCIO4 V REF2(4) V REF1(0) GND Bank 0 V CCIO0 V REF2(0) V REF1(1) GND Bank 1 V CCIO1 V REF2(1)

45 Technical Seminar Tour Page 44 MachXO / XP / Overview DDR Memory Interfaces DDR DRAM is the Low-Cost Memory of Choice –>50% of 2004 Total DRAM Bits DDR Memory Interface Issues –Bi-directional DQ & DQS –Tight timing specifications –Clock domain transfers –Muxing/de-muxing data LatticeXP Pre-Engineered DDR Interfaces Precision DQS Delay Control (Temp. & Voltage-Compensated) Dedicated DDR Registers (Fast Muxing/Demuxing) Automatic DQS to System Clock Domain Transfer Half Clock Transfer High-Performance 166MHz 333Mbps Exceptional DDR Performance Automatic Clock Transfer Circuitry Simplifies Design & Ensures Robust Operation DDR to SDR De-mux Half Clock Transfer DLL Calibrated DQS to DQ Alignment DQS Data DQS Clock DDRCLKPOL DQS Delay Block* Clock Polarity Select* Input Logic Block * Selected Input Logic Blocks

46 Technical Seminar Tour Page 45 MachXO / XP / Overview Multiple Power Supply Options Use C Version to Access Latest Technology Without Adding New Power Supplies to Board –Improve performance and power consumption –Allows single supply operation from 3.3-volts Use E Version to Minimize Power Consumption –64% lower power than operation at 3.3-volts Lower Voltage (E) Version V CC V CCP V CCAUX V CCJ V CCIO 1.2 to 3.3V for Chosen I/O Std. 1.2 Volts3.3 Volts Upper Voltage (C) Version V CC V CCP V CCAUX V CCJ V CCIO 1.2 to 3.3V for Chosen I/O Std. 3.3/2.5/1.8 Volts3.3 Volts Internal logic operates at 1.2-volts

47 Technical Seminar Tour Page 46 MachXO / XP / Overview Sleep Mode Reduces Power by Factor of 1000 Mode CharacteristicNormalOffSleep SLEEPN PinHighXLow Static IccTypical <100mA0Typical <100uA Power SuppliesNormal RangeOffNormal Range Logic OperationUser DefinedNon Operational I/O OperationUser DefinedTri-State Lattice XP SLEEPN Pin Device State NormalSleep ModeNormal Typical 100nSTypical 2mS Note: Sleep Mode is only available on 1.8/2.5/3.3V C version

48 Technical Seminar Tour Page 47 MachXO / XP / Overview 0% 10% 20% 30% 40% 50% 60% 70% 80% LVCMOS PCI LVTTL LVDS LVPECL SSTL PCI-X HSTLHT/LDT % Of High Volume Designs Optimizing I/O Capability 100%50%100%50%0%*100%0%100%0% Percentage of XP I/O Supporting * Can be supported through emulation Low Implementation Cost High Implementation Cost Optimized I/O Support Delivers Uncommon Value

49 Technical Seminar Tour Page 48 MachXO / XP / Overview LatticeXP Benefits Self-Configuration in Under A Millisecond Ideal for system heartbeat control logic Supports configuration scrubbing for SEU control Supports rapid power cycling High Security Security bits prevent readback No exposed power-up bitstream Single Chip Simplify design Reduced PCB footprint Save boot PROM costs SRAM + FLASH Real time programming of device during operation On-Chip Regulation Support legacy applications with latest technology - Reduce costs - Improve performance

50 Technical Seminar Tour Page 49 MachXO / XP / Overview LatticeXP Family DeviceXP3XP6XP10XP15XP20 LUTs (K) sysMEM Blocks sysMEM (Kbits) Distributed RAM (Kbits) Voltage (V) 1.2/1.8/2.5/3.3V PLLs22444 Package I/O Combinations 100-pin TQFP (14x14mm) pin TQFP (20x20mm) pin PQFP (28x28mm) ball fpBGA (17x17mm) ball fpBGA (23x23mm) ball fpBGA (23x23mm)300340

51 Technical Seminar Tour Page 50 MachXO / XP / Overview LatticeXP Value Proposition Non-Volatile FPGA –Single Chip –High Security –Instant-On Mainstream LUT-based Architecture Optimized Device Provides Low Cost Solution –Manufacturable 130nm silicon process Best DDR Memory Support –Easy design of 333Mbps interfaces Popular Packaging Options –TQFP, PQFP, fpBGA –RoHS / Lead-Free available Combines the Best of Non-Volatile & SRAM -- No Compromise FPGA!

52 Technical Seminar Tour Page 51 MachXO / XP / Overview Lattice Product Families Density I/O LatticeECP/2/XP/ FPGA MachXO Crossover ispMACH CPLD LatticeSC System Chip

53 Technical Seminar Tour Page 52 MachXO / XP / Overview

54 Technical Seminar Tour Page 53 MachXO / XP / Overview LatticeSC Architecture High Performance FPGA Fabric 4 to 32 SERDES (Up to 3.4Gbps) with Physical Coding Sublayer (PCS) 15K to 115K LUT4s System-Level Features: Embedded System Bus / Dedicated Microprocessor Interface / SPI Flash Configuration 2Gbps PURESPEED I/O Up to 7.8 Mbits of Embedded Memory Blocks MACO: Embedded Structured ASIC Blocks (LatticeSCM Devices) 8 Analog PLLs / 12 DLLs per Device 1.0V-1.2V Operating Voltage

55 Technical Seminar Tour Page 54 MachXO / XP / Overview Masked Array for Cost Optimization Multiple 90nm Embedded 50K ASIC Blocks Ample FPGA-to-ASIC Signal Connectivity Ample ASIC-to-IO Connectivity High-speed Clock Connectivity

56 Technical Seminar Tour Page 55 MachXO / XP / Overview MACO: Standard Offerings LatticeSCM25 EMBC D AB PLC Array EMBE MACO SERDES Quad SERDES Quad SERDES Quad SERDES Quad F A A B B C C C

57 Technical Seminar Tour Page 56 MachXO / XP / Overview LatticeSC(M) Family DeviceSC15SC25SC40SC80SC115 LUTs (K) sysMEM Blocks (18Kb) Embedded Memory (Mbits) Distributed Memory (Mbits) Gbps SERDES PLLs / DLLs8 / 12 MACO Blocks* Package I/O + SERDES Combinations (1mm Ball Pitch) 256-ball fpBGA (17x17) ball fpBGA (31x31) ball ffBGA (33x33) ball fcBGA (35x35) ball fcBGA (42.5x42.5) *Maximum Number of 50K Gate MACO Blocks. MACO Enabled Only on LatticeSCM Family

58 Technical Seminar Tour Page 57 MachXO / XP / Overview ispLEVER ® Design Tools OEM Tools integrated: Mentor Graphics Precision Synplicity Synplify Model Technologie ModelSim

59 Technical Seminar Tour Page 58 MachXO / XP / Overview ispLEVER ® Design Tools Unified GUI –FPGA / FPSC / CPLD / SPLD PC, UNIX and LINUX Versions Integrated 3rd Party Synthesis and Simulation Tools –Mentor Graphics –Synplicity Free ispLEVER-starter will support every PLD device –VHDL & Verilog Synthesis –Schematic –Module / IP manager –ispTracy Logic Analyzer –Simulator –Floor Planner –Pin Editor Mapping / Packing Mapping / Packing Delay File Design Database Design Database Floorplanner IP Manager The Simple Machine for Complex Designs Logic Simulation and Timing Verification Logic Simulation and Timing Verification Design Synthesis HDL Capture and Simulation Simulation Timing Analyzer Fitting / Place & Route Fitting / Place & Route

60 Technical Seminar Tour Page 59 MachXO / XP / Overview ispLEVER Configuration Options Device SupportSynthesi s Support SimulationLicense Type ispLEVER - Stand-Alone Compiler All Lattice Programmable Logic: All Devices n/a Floating (UNIX/LINUX) Node Locked or Floating (PC) Includes Lattice device libraries to work with 3rd party EDA environments. (PC, UNIX) ispLEVER Base HDL All DevicesMentor Precision 2005b Synplicity Synplify 8.2h ModelSim 6.1a Lattice Functional Simulator Node Locked or Floating ispLEVER Starter New / Focus CPLD,MachXO, XPGA,GDX EC, ECP, XP3-XP6 Mentor Precision 2005b Synplicity Synplify 8.2h Lattice Functional Simulator Node Locked: 6-Month Trial Intended for evaluation, and student users, ispLEVER Starter is a complete solution that can take your design from concept through device programming. (PC) Free SW Für SeminarTeilnehmer: 295

61 Technical Seminar Tour Page 60 MachXO / XP / Overview ispTRACY Debugging Environment

62 Technical Seminar Tour Page 61 MachXO / XP / Overview Lattice IP Support PCI DDR I 1GB Ethernet MAC 10/100 Ethernet MAC QDR II SDRAM DMA I 2 C ….. and more see Evaluation Board Allows Many IPs to Be Checked Out In The Lab

63 Technical Seminar Tour Page 62 MachXO / XP / Overview JumpIn2Practice by eVision Systems Get your ideas into the market, FAST - F PGA relevant Training content - A ll tutorials based on ispLEVER - S upport you with BASIC and ADVANCED Course - T raining Material that will become your day to day working book for the future YOUR SUCCESS IS OUR MISSION

64 Technical Seminar Tour Page 63 MachXO / XP / Overview JumpIn2Practice About eVision Systems - independent EDA Company based in the Munich area - VHDL, Verilog and SystemC Tools - RFIC & MICROWAVE Design Tools - Technical Support Team - Training Services - Own HDL Design Experience


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