1. FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved What are FPGA Power Management Software Options?

2. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 2 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 2 © 2009 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to:  Explain some of the built in features that are already built into the ISE software  Use the XST, MAP, and PAR options to manage power consumption

3. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 3 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 3 © 2009 Xilinx, Inc. All Rights Reserved Software Power Optimization Roadmap 2006 XPE power estimator XPower Analyzer Power optimized routing ISE8.2i 2007 XPE power estimator XPower Power optimized routing Power optimized synthesis Power optimized placer LUT power reduction (Virtex-5) New XPA GUI (EA) ISE9.1/2i ISE10.1i Early 2008 XPE power estimator XPower Analyzer Power optimized routing Power optimized synthesis Power optimized placer LUT power reduction Activity based power Optimization Power optimized BRAM (sp3) ISE11.1i Early 2009 XPE power estimator XPower Analyzer Power optimized routing Power optimized synthesis Power optimized placer LUT power reduction Activity based power optimization Power optimized BRAM BUFGCE automatic generation FF packing onto minimum clock leaves More clock gating enhancements More synthesis enhancements  Xilinx has a long history in power optimization software

4. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2009 Xilinx, Inc. All Rights Reserved Power Optimizations in ISE  Power optimizations – Clock power reduction in placement FF packing onto Minimum Clock Leaves – Power-aware LUT mapping – Clock gating Automatic use of the BUFGCE function in Virtex-4, Virtex-5, Spartan-3A/3ADSP New clock gating features (BUFHCE) – Power-aware synthesis (cluster high-activity nets in common slices) Minimizes net delay  Older power optimizations – -lc auto (switch in MAP) allows splitting of LUT6 into two LUT5 – Reduce capacitance for non-timing critical nets – Minimize wire lengths/capacitance Prevents duplication of logic – Reprogram LUT functions to reduce toggling nodes Product Architecture Dedicated Hard IP SW Power Optimization SW Power Optimization Process Technology Low Power Design Techniques Power Estimation Tools Power Estimation Tools SW Power Optimization

5. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Design Goals & Strategies  Right-click on Synthesize-XST and select Design Goals & Strategies  Sets various options for XST, MAP, and PAR for power optimization – XST: Optimization Goal = Area – XST: Power Reduction = True – MAP: Power Reduction = True – PAR: Power Reduction = True – …and other options

6. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Synthesis Options  Right-click on Synthesize-XST  Process Properties (default options shown)  Optimization Goal – (Area) – Reduces the overall amount of logic in the design – This will hurt speed  Power Reduction – (when checked) – XST optimizes the design to consume as little power as possible

7. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved Other Synthesis Options  Over-constraining (making timing constraints unnecessarily tight) during synthesis can significantly increase register use – Seen as an average increase from 1–5 percent – Do NOT over-constrain during synthesis  Global optimization can lead to mixed results – Can achieve ~10 percent flip-flop reduction Gives back much of the utilization benefits (and sometimes more) due to control signal generation  FSM optimization – Turning off FSM optimization can yield a small flip-flop savings – One-hot encoding is not as useful  Try turning the Logic Replication synthesis option off  This is normally used to reduce net delays of high-fanout nets

8. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved MAP Options  Right-click on Map  Process Properties (default options shown)  Power Reduction – (when checked) – Enables timing driven packing to minimize routing  Power Activity File – (when Power Reduction is checked) – Allows you to specify a VCD or SAIF file to guide map – This file is an output from simulation – Allows MAP to set frequencies and activity rates for internal signals

9. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved PAR Options  Right-click on Place & Route  Process Properties (default options shown)  Power Reduction – (when checked) – Optimizes routing to enable power reduction  Power Activity File – (when Power Reduction is checked) – Allows you to specify a VCD or SAIF file to guide map – This file is an output from simulation – Allows PAR to set frequencies and activity rates for internal signals

10. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved Power Optimization in ISE  ISE v11.1 test results on a customer design (Virtex-5 LX110T) –9% average Predicted Power Reduction –18% dynamic power reduction for Vccint –13% Static and Dynamic Power for Vccint  Customer Measured Board-Level Power Results –~ 13% Total Power Reduction

11. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved Summary  Setting the Design Goals & Strategies option to Power Optimization makes all the necessary setting your need – XST and the ISE software contain numerous options that WILL reduce your design’s power consumption – As new optimizations are built into the software, this will continue to be the best way to enable power optimization  Associate a Power Activity File to enable the tools to optimize your system’s dynamic power consumption  Power optimization settings may hurt your design speed – Always use timing constraint to allow the tools to improve your system timing

12. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More?  Xilinx Software Manuals (online or from ISE Help) – www.support.xilinx.com www.support.xilinx.com Command Line User Guide – Explains Power Optimization settings for Map and PAR XST User Guide – Explains Power Optimization settings

13. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More?  Xilinx Training www.xilinx.com/training www.xilinx.com/training – Designing with Spartan-6 and Virtex-6 Device Families course How to get the most out of both device families How to build the best HDL code for your FPGA design How to optimize your design for Spartan-6 and/or Virtex-6 How to take advantage of the newest device features  Free Video Based Training – How Do I Plan to Power My FPGA? – Power Estimation – What are the Spartan-6 Power Management Features? – What are the Virtex-6 Power Management Features? – What are FPGA Power Management HDL Coding Techniques?

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