1. 1 Digital Logic Design Week 7 Decoders, encoders and multiplexers

2. 2 Decoders Encoders Multiplexers Decoders, encoders and multiplexers

3. 3 Decoders Decoder detects the presence of specific combinations of bits (code) at its input  Indicates presence of code by asserting outputs: active-HIGH or active-LOW Example: two simple decoders that detect the presence of the binary code 0011 A1A1 A0A0 A2A2 A3A3 X active-HIGH decoder for 0011 A1A1 A0A0 A2A2 A3A3 X active-LOW decoder for 0011 (LSB) (MSB)

4. 4 A simple decoder 1 1 1 0 1 What binary number does this decoder detect? Boolean expression for the decoder output? Active-LOW or active-HIGH output?

5. 5 3-to-8 decoder inputs 3-to-8 decoder binary number detected  General decoders have n inputs and 2 n outputs – Precisely one output asserted for each unique bit pattern

6. 6 Decoders with active-LOW outputs  Active-LOW outputs are indicated by “bubbles” on decoder outputs Inputs Outputs 4-to-16 decoder 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 What are the decoder outputs for the inputs shown?

7. 7 Decoders with enable input  Enable input is like an on/off switch for the decoder:  E=1: decoder functions “normally” → one output asserted  E=0: no outputs asserted inputs 2-to-4 decoder E (enable) outputs EA 1 A 0 D 0 D 1 D 2 D 3 ----------------------------------------------- 00 0 0 0 0 0 00 1 0 0 0 0 01 0 0 0 0 0 01 1 0 0 0 0 10 0 1 0 0 0 10 1 0 1 0 0 11 0 0 0 1 0 11 1 0 0 0 1 E=0E=1

8. 8 Logisim simulation of 74x138

9. 9 Decoder application #1 Input/output (I/O) devices exchange data with microprocessor via a shared data bus At most one I/O device uses data bus at any one time Each I/O device has: – unique “address” A 3 A 2 A 1 A 0 – active-LOW enable input (EN) A 3 A 2 A 1 A 0 inputs to 4-to-16 decoder Sixteen possible 4-bit I/O port addresses – 0000,0001,…,1111 – ports 0–6 (decimal) used here – ports 7–15 (decimal) unused

10. 10 Decoder application #2  Recall: each decoder output corresponds to a minterm  To produce a sum of minterms expression, simply OR together the relevant decoder outputs! 3-to-8 decoder

11. 11 Decoder application #2 A B C in C out S ------------------------------------------- 0 0 0 00 0 0 1 01 0 1 0 01 0 1 1 10 1 0 0 01 1 0 1 10 1 1 0 10 1 1 1 11 Example: Full-adder adds three bits: A, B and carry-in (C in )  Result is sum (S) and carry-out (C out )

12. 12 Decoder-based implementation of full-adder Decoder outputs 1,2,4,7 Decoder outputs 3,5,6,7

13. 13 Decoders Encoders Multiplexers Decoders, encoders and multiplexers

14. 14 inputs 16-to-4 encoder outputs Encoders  Encoders perform “reverse” of decoder function  Assume only one input is asserted, then output is binary code for that input  Example: if D 7 is the only HIGH input, then A 3 A 2 A 1 A 0 = 0111  In general: input D k asserted → output is binary equivalent of decimal k

15. 15 Encoder application: keypad encoding Keypad input 16-to-4 encoder Binary code representing key pressed What should an encoder do if multiple inputs are active? One answer: make the device a priority encoder respond to the highest-priority input that is active, and ignore any lower priority inputs

16. 74x148 : priority encoder  Active-LOW inputs 0,1,2,…,7  7: highest priority  0: lowest priority  Coded output A 2 A 1 A 0  highest asserted input is  Active-LOW enable input EI  GS and EO outputs not important here

17. 74x148 : priority encoder

18. 18 Decoders Encoders Multiplexers Decoders, encoders and multiplexers

19. 19 Multiplexers A multiplexer (MUX) routes data from one of the data inputs D 0, D 1, D 2, D 3 to the output Y Select inputs S 1 and S 0 determine which data input is chosen

20. 20 Multiplexer – timing diagram

21. 21 Multiplexer (MUX) Data input selected by S 1 S 0 is directed to output Y S 1 S 0 = 00 : Y = D 0 S 1 S 0 = 01 : Y = D 1 S 1 S 0 = 10 : Y = D 2 S 1 S 0 = 11 : Y = D 3 Y S 1 S 0 D0D0 D1D1 D2D2 D3D3 4-to-1 MUX

22. 74x151 : 8-to-1 MUX

23. MUX application #1 When A 2 A 1 A 0 = 000, Y = D 0 → set D 0 = 0 When A 2 A 1 A 0 = 001, Y = D 1 → set D 1 = 1 Y S2S2 D0D0 D1D1 D2D2 D3D3 8-to-1 MUX D4D4 D5D5 D6D6 D7D7 S1S1 S0S0 A 2 A 1 A 0 Y -------------------------- 0 0 0 0D 0 0 0 1 1D 1 0 1 0 0D 2 0 1 1 1D 3 1 0 0 0D 4 1 0 1 1D 5 1 1 0 1D 6 1 1 1 0D 7 Use an 8-to-1 MUX to implement the Boolean function in the truth table below A2A1A0A2A1A0

24. MUX application #1 Data inputs tied LOW (= logic-0)  0,2,4,7 Data inputs tied HIGH (= logic-1)  1,3,5,6 Compare with truth table on previous page

25. MUX application #2 Time-division multiplexing (TDM) – Multiple bit-streams share access to channel by “taking turns” – Sub-channel #1 in time slot 1, sub-channel #2 in time slot 2, … TDM also used by second-generation (2G) mobile phones (GSM) to share access to radio spectrum Data input rate on each “sub-channel” is 64kbits/s High-speed channel data rate = 8×64 = 512 kbits/s

26. 26 Demultiplexer (DEMUX) Data input is directed to the output line selected by S 1 S 0 S 1 S 0 = 00 : data input to D 0 S 1 S 0 = 01 : data input to D 1 S 1 S 0 = 10 : data input to D 2 S 1 S 0 = 11 : data input to D 3 Non-selected output lines have LOW levels Data input S 1 S 0 D0D0 D1D1 D2D2 D3D3 1-to-4 DEMUX

27. 27 Demultiplexer – timing diagram

28. 28 DEMUX = decoder with enable DS 1 S 0 D 0 D 1 D 2 D 3 ----------------------------------------------- 00 0 0 0 0 0 00 1 0 0 0 0 01 0 0 0 0 0 01 1 0 0 0 0 10 0 1 0 0 0 10 1 0 1 0 0 11 0 0 0 1 0 11 1 0 0 0 1 D=0D=1 D S 1 S 0 D0D0 D1D1 D2D2 D3D3 1-to-4 DEMUX 2-to-4 decoder E (enable)