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5.5 Encoders ReturnNext A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and.

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Presentation on theme: "5.5 Encoders ReturnNext A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and."— Presentation transcript:

1 5.5 Encoders ReturnNext A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The output code generally has fewer bits than the input code, and there is one-to-one mapping from input code words into output code words. input code word output code word enable inputs map Encoder

2 5.5 Encoders Binary encoder  The most common decoder circuit is an 2 n -to- n encoder or binary encoder. Such a encoder has an 2 n -bit binary input code and n- bit output binary code. NextBackReturn Binary encoder I0 Y0 I1 Y1 I2 : : : : Y n-1 I2 n-1 Write the truth table for 8-to-3 binary encoder and the output logic function expressions.

3 If multiple requests can be made simultaneously, the encoder gives undesirable results. 5.5 Encoders NextBackReturn Simulation Suppose the inputs I2 and I4 are both 1, what is the output ?

4 Priority Encoders The solution is to assign priority to the input lines, so that when multiple inputs are asserted, the encoding device produces the number of the highest-priority input. Such a device is called a priority encoder. 5.5 Encoders NextBackReturn The 74x148 Priority Encoders EI I7 A2 I6 A1 I5 A0 I4 I3 GS I2 EO I1 I0 74X

5 Input data I0-I7 Enable input EI Output GS is asserted when the device is enabled and one or more of the request are asserted. Output EO is asserted if EI is assert but no request input is asserted, it designed to be connected to the EI input of another ‘ 148 that handles lower-priority requests. 5.5 Encoders NextBackReturn

6 Truth table for a 74x148 8-input priority encoder 5.5 Encoders NextBackReturn InputsOutputs EI I0 I1 I2 I3 I4 I5 I6 I7A2 A1 A0 GS EO 1 x x x x x x x x 0 x x x x x x x 0 0 x x x x x x x x x x x x x x x x x x x x x

7 Logic diagram for the 74x148 priority encode (p379 Figure 5-50) 5.5 Encoders BackReturn Cascading Binary Encoders (p380 Figure 5-51)


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