# COE 202: Digital Logic Design Combinational Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Ahmad Almulhem, KFUPM.

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COE 202: Digital Logic Design Combinational Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Ahmad Almulhem, KFUPM 2009

Objectives Decoders Encoders Multiplexers DeMultiplexers Ahmad Almulhem, KFUPM 2009

Functional Blocks Digital systems consists of many components (blocks) Useful blocks needed in many designs Arithmetic blocks Decoders Encoders Multiplexers Ahmad Almulhem, KFUPM 2009 iPhone motherboard (torontophonerepair.com)

Decoder Information is represented by binary codes Decoding - the conversion of an n-bit input code to an m-bit output code with n <= m <= 2 n such that each valid code word produces a unique output code Circuits that perform decoding are called decoders A decoder is a minterm generator Ahmad Almulhem, KFUPM 2009....... n inputs2 n outputs n-to-2 n Decoder

Decoder (Uses) Decode a 3-bit op-codes:Home automation: Ahmad Almulhem, KFUPM 2009 3-to-8 Decoder Add Sub And Xor Not Load Store Jump op0 op1 op2 2-to-4 Decoder Light A/C Door Light-A/C C0C1C0C1 Load a Add b Store c.

Decoder with Enable Ahmad Almulhem, KFUPM 2009 A decoder can have an additional input signal called the enable which enables or disables the output generated by the decoder...... 2 n outputs n-to-2 n Decoder Enable bit. n inputs

2-to-4 Decoder A 2-to-4 Decoder 2 inputs (A 1, A 0 ) 2 2 = 4 outputs (D 3, D 2, D 1, D 0 ) Ahmad Almulhem, KFUPM 2009

2-to-4 Decoder A 2-to-4 Decoder 2 inputs (A 1, A 0 ) 2 2 = 4 outputs (D 3, D 2, D 1, D 0 ) Truth Table A1A1 A0A0 D0D0 D1D1 D2D2 D3D3 001000 010100 100010 110001 Ahmad Almulhem, KFUPM 2009

2-to-4 Decoder A 2-to-4 Decoder 2 inputs (A 1, A 0 ) 2 2 = 4 outputs (D 3, D 2, D 1, D 0 ) Truth Table A1A1 A0A0 D0D0 D1D1 D2D2 D3D3 001000 010100 100010 110001 Src: Mano’s book Ahmad Almulhem, KFUPM 2009

2-to-4 Decoder with Enable Ahmad Almulhem, KFUPM 2009 ENA1A1 A0A0 D0D0 D1D1 D2D2 D3D3 0XX0000 1001000 1010100 1100010 1110001 Truth Table

2-to-4 Decoder with Enable Ahmad Almulhem, KFUPM 2009 ENA1A1 A0A0 D0D0 D1D1 D2D2 D3D3 0XX0000 1001000 1010100 1100010 1110001 Src: Mano’s book Truth Table

3-to-8 Decoder Ahmad Almulhem, KFUPM 2009 3-to-8 Decoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2

3-to-8 Decoder Ahmad Almulhem, KFUPM 2009 A2A2 A1A1 A0A0 D0D0 D1D1 D2D2 D3D3 D4D4 D5D5 D6D6 D7D7 00010000000 00101000000 01000100000 01100010000 10000001000 10100000100 11000000010 11100000001 3-to-8 Decoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2

3-to-8 Decoder Ahmad Almulhem, KFUPM 2009 3-to-8 Decoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2

3-to-8 Decoder (using 2 2-to-4 decoders) Ahmad Almulhem, KFUPM 2009 3-to-8 Decoder 2-to-4 Decoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 2-to-4 Decoder D0D1D2D3D0D1D2D3 D4D5D6D7D4D5D6D7 A0A1A0A1 A0A1A0A1 A2A2 E E

Decoder-Based Combinational Circuits A Decoder generates all the minterms A boolean function can be expressed as a sum of minterms Any boolean function can be implemented using a decoder and an OR gate. Note: The Boolean function must be represented in terms of its minterms and not its minimized form Ahmad Almulhem, KFUPM 2009

Decoder-Based Combinational Circuits (Example) Ahmad Almulhem, KFUPM 2009 XYZCS 00000 00101 01001 01110 10001 10110 11010 11111 S = ∑m (1,2,4,7) C = ∑m (3,5,6,7) 3 inputs and 8 possible minterms 3-to-8 decoder can be used for implementing this circuit

Decoder-Based Combinational Circuits (Example) Ahmad Almulhem, KFUPM 2009 Src: Mano’s book XYZCS 00000 00101 01001 01110 10001 10110 11010 11111 S = ∑m (1,2,4,7) C = ∑m (3,5,6,7) 3 inputs and 8 possible minterms 3-to-8 decoder can be used for implementing this circuit

Decoder-Based Combinational Circuits (Summary) Good if: Many output functions with same inputs Each output has few minterms Hint: Check if the function complement has fewer minterms and use NOR instead of OR. Ahmad Almulhem, KFUPM 2009

Encoder Encoding - the opposite of decoding - the conversion of an m- bit input code to a n-bit output code with n  m  2 n such that each valid code word produces a unique output code Circuits that perform encoding are called encoders An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears........ n outputs 2 n inputs 2 n -to-n Encoder Ahmad Almulhem, KFUPM 2009

8-to-3 Encoder Description: 2 3 = 8 inputs, 3 outputs one input =1, others = 0’s Each input generate unique binary code Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2

8-to-3 Encoder (truth table) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111

8-to-3 Encoder (truth table) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 1000000010000000 000000 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111

8-to-3 Encoder (truth table) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 0100000001000000 100100 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111

8-to-3 Encoder (truth table) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 0000010000000100 101101 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111

8-to-3 Encoder (truth table) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 0000000100000001 111111 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111

8-to-3 Encoder (equations) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111 Note: This truth table is not complete! Why? Output equations: A 0 = ? A 1 = ? A 2 = ?

8-to-3 Encoder (equations) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111 Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = ? A 2 = ?

8-to-3 Encoder (equations) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111 Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = ?

8-to-3 Encoder (equations) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111 Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7

8-to-3 Encoder (circuit) Ahmad Almulhem, KFUPM 2009 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7 A0A1A2A0A1A2 D1D3D5D7D1D3D5D7 D2D3D6D7D2D3D6D7 D4D5D6D7D4D5D6D7

8-to-3 Encoder (limitations) Ahmad Almulhem, KFUPM 2009 Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111 Two Limitations: 1. Two or more inputs = 1 Example: D 3 = D 6 = 1 A 2 A 1 A 0 = 111 2.All inputs = 0 Same as D 0 =1

Priority Encoder Address the previous two limitations 1.Two or more inputs = 1 Consider the bit with highest priority 2.All inputs = 0 Add another output v to indicate this combination Ahmad Almulhem, KFUPM 2009

4-to-2 Priority Encoder Ahmad Almulhem, KFUPM 2009 Description: 2 2 = 4 inputs, 2 + 1 outputs Two or more 1’s take highest priority

4-to-2 Priority Encoder Ahmad Almulhem, KFUPM 2009 inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX0 0001001 001X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, 2 + 1 outputs Two or more 1’s take highest priority This is a condensed truth table! It has only 5 rows instead of 16! Row 3 = 2 combinations Row 4 = 4 combinations Row 5 = 8 combinations

4-to-2 Priority Encoder Ahmad Almulhem, KFUPM 2009 inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX0 0001001 001X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, 2 + 1 outputs Two or more 1’s take highest priority

4-to-2 Priority Encoder Ahmad Almulhem, KFUPM 2009 inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX0 0001001 001X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, 2 + 1 outputs Two or more 1’s take highest priority Equations: A 0 = D 3 + D 1 D 2 ’ A 1 = D 2 + D 3 V= D 0 + D 1 + D 2 + D 3

4-to-2 Priority Encoder Ahmad Almulhem, KFUPM 2009 inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX0 0001001 001X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, 2 + 1 outputs Two or more 1’s take highest priority Equations: A 0 = D 3 + D 1 D 2 ’ A 1 = D 2 + D 3 V= D 0 + D 1 + D 2 + D 3

Multiplexers Is a combinational circuit Has a single output Directs one of 2 n input to the output Input to output direction is done based on a set of n select bits Ahmad Almulhem, KFUPM 2009 2 n inputs n select lines one output 2 n x 1 MUX

2x1 MUX A 2x1 multiplexer (MUX) will have 2 input lines and 1 select line Y=D 0 for S 0 =0, and Y=D 1 for S 0 =1 Minimizing will result in: Y = S 0 ’.D 0 + S 0.D 1 Ahmad Almulhem, KFUPM 2009 S0S0 D0D1D0D1 Y 2x1 MUX

4x1 MUX A 4x1 MUX will have 4 input lines (D 0, D 1, D 2, D 3 ) and 1 output Y with 2 Select Lines (S 0, S 1 ) The output for different select values is defined as: S 0 S 1 = 00, Y = D 0 S 0 S 1 = 01, Y = D 1 S 0 S 1 = 10, Y = D 2 S 0 S 1 = 11, Y = D 3 Y = S 1 S 0 D 0 + S 1 S 0 D 1 + S 1 S 0 D 2 + S 1 S 0 D 3 The output Y depends on the minterms of the Select lines Ahmad Almulhem, KFUPM 2009 S 1 S 0 D0D1D2D3D0D1D2D3 Y 4x1 MUX

Quad 2x1 MUX Does multiplexing of two 4-bit numbers. Has a 4-bit output and a single select line Is built using four 2x1 MUXes Ahmad Almulhem, KFUPM 2009 S0S0 A0B0A0B0 Y0Y0 2x1 MUX S0S0 A2B2A2B2 Y2Y2 S0S0 A1B1A1B1 Y1Y1 S0S0 A3B3A3B3 Y3Y3

Quad 2x1 MUX Ahmad Almulhem, KFUPM 2009 S0S0 A0A1A2A3A0A1A2A3 B0B1B2B3B0B1B2B3 Y0Y1Y2Y3Y0Y1Y2Y3 QUAD 2X1 MUX Y = A If S 0 = 0 Y = B if S 0 =1

MUX-based Design A MUX can be used to implement any function expressed using its minterms Example: Implement F(A,B,C)=∑(1,3,5,6) using MUXes Solution1: We can use a MUX with the number of select lines equal to the number of input variables of the function. Since this function has 3 input variables, it will require 3 select lines, i.e. an 8x1 MUX Ahmad Almulhem, KFUPM 2009

MUX-based Design (n-Select lines) Ahmad Almulhem, KFUPM 2009 D0D1D2D3D0D1D2D3 D4D5D6D7D4D5D6D7 Y 01100110 01010101 S 0 S2S2 S1S1 A B C F(A,B,C)=∑(1,3,5,6) ABCF 0000 0011 0100 0111 1000 1011 1101 1110

MUX-based Design (n-1 Select lines) Implement the function F(A,B,C) =∑(1,3,5,6) We will use 2 select lines instead of the 3 required for the three input variables A => S1, B=> S0 The third variable C and its complement will serve as two of the inputs to the MUX Ahmad Almulhem, KFUPM 2009

MUX-based Design (n-1 Select lines) Ahmad Almulhem, KFUPM 2009 ABCF 0000 F = C 0011 0101 F = C’ 0110 1000 F = 0 1010 1101 F = 1 1111 D0D1D2D3D0D1D2D3 F S1S1 S0S0 A B C C’ 0 1 F(A,B,C)=∑(1,3,5,6)

Another Example Implement the function F(A,B,C,D)=∑(1,3,4,11,12,13,14,15) We can implement this function with 3 Select lines => an 8x1 MUX is required Ahmad Almulhem, KFUPM 2009

ABCDF 00000 F = D 00011 00100 00111 01001 F = D’ 01010 01100 F = 0 01110 10000 10010 10100 F = D 10111 11001 F = 1 11011 11101 11111 D0D1D2D3D0D1D2D3 D4D5D6D7D4D5D6D7 D 0 1 8x1 MUX F A B C S2S2 S1S1 S0S0 Example

DeMultiplexer Performs the inverse of the operation of a MUX It has one input line, the input from which is transmitted to one of 2n output lines The output lines are selected based on the select inputs Ahmad Almulhem, KFUPM 2009 E 1x2 DeMUX S D0D1D0D1

1x4 DeMUX The circuit has an input E, the outputs are given by: D 0 = E, if S 0 S 1 =00 D 0 = S 1 ’S 0 ’ E D 1 = E, if S 0 S 1 =01 D 1 = S 1 ’S 0 E D 2 = E, if S 0 S 1 =10 D 2 = S 1 S 0 ’ E D 3 = E, if S 0 S 1 =11 D 3 = S 1 S 0 E Ahmad Almulhem, KFUPM 2009 E 1x4 DeMUX S 0 S 1 D0D1D2D3D0D1D2D3

DeMUX/Decoder The circuit diagram of a 1x4 DeMUX resembles a 2x4 Decoder with an Enable input For the decoder, the inputs are A 1 and A 0, and the signal E is the Enable For the DeMUX, the inputs S 1 and S 0 are the select inputs and E is the actual input Ahmad Almulhem, KFUPM 2009 D0D0 D1D1 D2D2 D3D3 S1S1 S0S0 E

Summary Useful Functional Blocks Decoders Encoders Multiplexers DeMultiplexers Can be used to build bigger systems Ahmad Almulhem, KFUPM 2009