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© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

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Presentation on theme: "© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic."— Presentation transcript:

1 © Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2003

2 © Digital Integrated Circuits 2nd Devices Goal of this chapter  Understand device operation for short- channel devices  Present intuitive understanding of device operation  Introduction of basic device equations  Introduction of models for manual analysis  Introduction of models for Spice/Spectre simulation  Analysis of secondary and deep-sub-micron effects  Understanding MOS transistor parasitics

3 © Digital Integrated Circuits 2nd Devices The Diode Mostly occurring as parasitic element in Digital ICs

4 © Digital Integrated Circuits 2nd Devices Depletion Region

5 © Digital Integrated Circuits 2nd Devices Diode Current

6 © Digital Integrated Circuits 2nd Devices Forward Bias (minority carrier concen.) Typically avoided in Digital ICs The diffusion current dominates the drift component. The carriers traverse the depletion region and are injected into to the neutral n and p regions (become minority carriers)

7 © Digital Integrated Circuits 2nd Devices Reverse Bias (minority carrier concen.) The Dominant Operation Mode for diode in CMOS VLSI design The drift current dominates the diffusion component. Barrier raised and almost no current from n to p. drift

8 © Digital Integrated Circuits 2nd Devices Models for Manual Analysis

9 © Digital Integrated Circuits 2nd Devices Junction Capacitance

10 © Digital Integrated Circuits 2nd Devices Diffusion Capacitance Caused by charge-storage effects of the minority carriers (in Forward-bias only)

11 © Digital Integrated Circuits 2nd Devices Secondary Effects –25.0–15.0–5.05.0 V D (V) –0.1 I D ( A ) 0.1 0 0 Avalanche Breakdown

12 © Digital Integrated Circuits 2nd Devices Diode Model

13 © Digital Integrated Circuits 2nd Devices SPICE Parameters

14 © Digital Integrated Circuits 2nd Devices What is a Transistor? A Switch! |V GS | An MOS Transistor

15 © Digital Integrated Circuits 2nd Devices The MOS Transistor Polysilicon Aluminum

16 © Digital Integrated Circuits 2nd Devices MOS Transistors -Types and Symbols D S G D S G G S DD S G NMOS PMOS B NMOS with Bulk Contact

17 © Digital Integrated Circuits 2nd Devices Threshold Voltage: Concept The semiconductor surface inverts to n-type material (strong inversion) A continuous n-type channel is formed

18 © Digital Integrated Circuits 2nd Devices The Threshold Voltage Fermi potential The value of V GS where strong inversion occurs is called the threshold voltage V T When V SB =0 (always has to be larger than -0.6V to back bias the pn-junction)

19 © Digital Integrated Circuits 2nd Devices The Body Effect

20 © Digital Integrated Circuits 2nd Devices Current-Voltage Relations A good transistor Quadratic Relationship 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T

21 © Digital Integrated Circuits 2nd Devices Transistor in Linear A continuous conductive channel <V GS -V T

22 © Digital Integrated Circuits 2nd Devices Transistor in Saturation Pinch-off constant

23 © Digital Integrated Circuits 2nd Devices Current-Voltage Relations Long-Channel Device Mobility (e.g. electron velocity)

24 © Digital Integrated Circuits 2nd Devices A model for manual analysis

25 © Digital Integrated Circuits 2nd Devices Current-Voltage Relations The Deep-Submicron Era Linear Relationship -4 V DS (V) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation

26 © Digital Integrated Circuits 2nd Devices Velocity Saturation  (V/µm)  c = 1.5  n ( m / s )  sat = 10 5 Constant mobility (slope = µ) Constant velocity (hole and electron) The critical field at which saturation occurs depends on both doping levels and vertical electrical field. Typically 1 to 5v/um for (2V across 0.25µm channel). 

27 © Digital Integrated Circuits 2nd Devices Perspective I D Long-channel device Short-channel device V DS V DSAT V GS - V T V GS = V DD When increasing the V DS, the electrical field in the channel ultimately reaches the critical value and the carriers at the drain become velocity saturated (gives a early saturation at V DSAT ).

28 © Digital Integrated Circuits 2nd Devices I D versus V GS 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V GS (V) I D (A) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) quadratic linear Long Channel Short Channel

29 © Digital Integrated Circuits 2nd Devices I D versus V DS -4 V DS (V) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T Long ChannelShort Channel

30 © Digital Integrated Circuits 2nd Devices A unified model for manual analysis of short-channel devices S D G B Linear (Resistive) V DS < V DSAT Saturated (Constant Current) V DS  V DSAT

31 © Digital Integrated Circuits 2nd Devices Simple Model versus SPICE V DS (V) I D (A) Velocity Saturated Linear Saturated V DSAT =V GT V DS =V DSAT V GT <V DSAT

32 © Digital Integrated Circuits 2nd Devices A PMOS Transistor -2.5-2-1.5-0.50 -0.8 -0.6 -0.4 -0.2 0 x 10 -4 V DS (V) I D (A) Assume all variables negative! VGS = -1.0V VGS = -1.5V VGS = -2.0V VGS = -2.5V

33 © Digital Integrated Circuits 2nd Devices Transistor Model for Manual Analysis

34 © Digital Integrated Circuits 2nd Devices The Transistor as a Switch Most time spent between here when discharging

35 © Digital Integrated Circuits 2nd Devices The Transistor as a Switch R is inversely proportional to W/L No significant reduction when V DD is much larger than V T +V DSAT /2 V DD can not be too small (e.g. close to V T ), otherwise resistance is very large

36 © Digital Integrated Circuits 2nd Devices The Transistor as a Switch

37 © Digital Integrated Circuits 2nd Devices MOS Capacitances Dynamic Behavior Dynamic behavior is a function of time for the transistor to charge/discharge the parasitic capacitances Parasitic includes  intrinsic capacitance of the device  load capacitance by the fanout gates and wires Intrinsic capacitance have three sources  basic MOS structure  channel charge  depletion region (of reversed-biased pn-junction at drain/source)

38 © Digital Integrated Circuits 2nd Devices Dynamic Behavior of MOS Transistor

39 © Digital Integrated Circuits 2nd Devices 1. The Gate Capacitance: overlap capacitance t ox n + n + Cross section view L eff Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap Source n + Drain n + W Lateral diffusion C GSO =C GDO = C ox X d W=C O W

40 © Digital Integrated Circuits 2nd Devices Cut-off ResistiveSaturation Most important regions in digital design: saturation and cut-off 2. The Gate Capacitance: channel capacitance

41 © Digital Integrated Circuits 2nd Devices Gate Capacitance Capacitance as a function of V GS (with V DS = 0) in linear region Capacitance as a function of the degree of saturation (V GS >V T ) Discontinuity at around V T + = V DSAT

42 © Digital Integrated Circuits 2nd Devices Measuring the Gate Cap using simulator I=C G (V GS ) dV GS /dt for V DS =0 ×10 -16

43 © Digital Integrated Circuits 2nd Devices 3. Junction Capacitance Bottom Side wall Channel Source N D Channel-stop implant N A SubstrateN A W x j L S Junction capacitance per unit area No channel side Junction capacitance per unit length

44 © Digital Integrated Circuits 2nd Devices Junction Capacitance Both C j and C jsw are non-linear and depends on the bias voltage. Keep large reverse-biased voltage for PN junction

45 © Digital Integrated Circuits 2nd Devices Capacitances in 0.25  m CMOS process

46 © Digital Integrated Circuits 2nd Devices The Sub-Micron MOS Transistor  Threshold Variations  Sub-threshold Conduction  Parasitic Resistances

47 © Digital Integrated Circuits 2nd Devices Threshold Variations due to DIBL V T L Long-channel threshold LowV DS threshold Threshold as a function of the length (for lowV DS ) Drain-induced barrier lowering (DIBL) (for very small )L V DS V T In traditional derivation of V T, the channel depletion region is assumed to mainly originate from gate voltage, which neglects the already depleted region in the source/drain area. This gives more error in case of shorter channel length.

48 © Digital Integrated Circuits 2nd Devices Threshold Variations due to Hot-carrier In short-channel devices, the increasing electric field causes increasing velocity of electron (until velocity saturation). Electron become too “hot”, often trapped in the oxide, which changes the threshold voltage. Hot-carrier effects typically increase threshold of NMOS, but decrease that of PMOS? This complicate the design and leads to long-term reliability problem.

49 © Digital Integrated Circuits 2nd Devices Sub-Threshold Conduction 00.511.522.5 10 -12 10 -10 10 -8 10 -6 10 -4 10 -2 V GS (V) I D (A) VTVT Linear Exponential Quadratic Typical values for S: 60.. 100 mV/decade The Slope Factor S is  V GS for I D 2 / I D 1 =10

50 © Digital Integrated Circuits 2nd Devices Sub-Threshold I D vs V GS V DS from 0 to 0.5V

51 © Digital Integrated Circuits 2nd Devices Sub-Threshold I D vs V DS V GS from 0 to 0.3V

52 © Digital Integrated Circuits 2nd Devices Summary of MOSFET Operating Regions (sub-micron design)  Strong Inversion V GS > V T  Linear (Resistive) V DS < V DSAT  Saturated (Constant Current) V DS  V DSAT  Weak Inversion (Sub-Threshold) V GS  V T  Exponential in V GS with linear V DS dependence

53 © Digital Integrated Circuits 2nd Devices Parasitic Resistances

54 © Digital Integrated Circuits 2nd Devices Latch-up Parasitic bipolar transistors exist and form positive feedback To cope with it, minimize the Nwell resistance and Psub resistance Place as many N-Well and Substrate contacts as possible To Backbias pn junction, body of PMOS connected to Vdd and body of NMOS to GND

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