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Digital System Design. Intro. VLSI: CMOS inverter.

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Presentation on theme: "Digital System Design. Intro. VLSI: CMOS inverter."— Presentation transcript:

1 Digital System Design

2 Intro. VLSI: CMOS inverter

3 CMOS inverter: black and white representation

4 A counter layout

5 Rules for design rule checking: basic rules

6 Rules for composition

7 Concept of the State Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS D FF Implementation T FF Implementation Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

8 State Behavior of R-S Latch Truth Table Summary of R-S Latch Behavior

9 Sequential Switching Networks Edge triggered device sample inputs on the event edge 7474 Bubble here for negative edge triggered device Positive edge-triggered flip-flop DQ Clk D-FlipFlop

10 Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register S,R are preset, preclear New value to first stage while second stage obtains current value of first stage Correct Operation, assuming positive edge triggered FF

11 Design Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?

12

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