1. Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/
Semiconductor Device Modeling and Characterization – EE5342 Lecture 37 – Spring 2011
Professor Ronald L. Carter

2. SPICE mosfet Model Instance CARM*, Ch. 4, p. 290
L = Ch. L. [m]
W = Ch. W. [m]
AD = Drain A [m2]
AS = Source A[m2]
NRD, NRS = D and
S diff in squares
M = device multiplier
©rlc L37-04May2011

3. CARM*, Ch. 4, p. 99
©rlc L37-04May2011

4. SPICE mosfet model levels
Level 1 is the Schichman-Hodges model
Level 2 is a geometry-based, analytical model
Level 3 is a semi-empirical, short-channel model
Level 4 is the BSIM1 model
Level 5 is the BSIM2 model, etc.
©rlc L37-04May2011

5. SPICE Parameters Level 1 - 3 (Static)
©rlc L37-04May2011

6. SPICE Parameters Level 1 - 3 (Static)
* 0 = aluminum gate, 1 = silicon gate opposite substrate type, 2 = silicon gate same as substrate.
©rlc L37-04May2011

7. SPICE Parameters Level 1 - 3 (Q & N)
©rlc L37-04May2011

8. Level 1 Static Const. For Device Equations
Vfb = -TPG*EG/2 -Vt*ln(NSUB/ni) q*NSS*TOX/eOx
VTO = as given, or
= Vfb + PHI + GAMMA*sqrt(PHI)
KP = as given, or
= UO*eOx/TOX
CAPS are spice pars., technological constants are lower case
©rlc L37-04May2011

9. Level 1 Static Const. For Device Equations
b = KP*[W/(L-2*LD)] = 2*K, K not spice
GAMMA = as given, or
= TOX*sqrt(2*eSi*q*NSUB)/eOx
2*phiP = PHI = as given, or
= 2*Vt*ln(NSUB/ni)
ISD = as given, or = JS*AD
ISS = as given, or = JS*AS
©rlc L37-04May2011

10. Level 1 Static Device Equations
vgs < VTH, ids = 0
VTH < vds + VTH < vgs,
id = KP*[W/(L-2*LD)]*[vgs-VTH-vds/2]
*vds*(1 + LAMBDA*vds)
VTH < vgs < vds + VTH,
id = KP/2*[W/(L-2*LD)]*(vgs - VTH)^2
*(1 + LAMBDA*vds)
©rlc L37-04May2011

11. SPICE Parameters Level 2
©rlc L37-04May2011

12. SPICE Parameters Level 2 & 3
©rlc L37-04May2011

13. Level 2 Static Device Equations
Accounts for variation of channel potential for 0 < y < L
For vds < vds,sat = vgs - Vfb - PHI
+ g2*[1-sqrt(1+2(vgs-Vfb-vbs)/g2]
id,ohmic = [b/(1-LAMBDA*vds)]
*[vgs - Vfb - PHI - vds/2]*vds
-2g[vds+PHI-vbs)1.5-(PHI-vbs)1.5]/3
©rlc L37-04May2011

14. Level 2 Static Device Eqs. (cont.)
For vds > vds,sat
id = id,sat/(1-LAMBDA*vds)
where id,sat = id,ohmic(vds,sat)
©rlc L37-04May2011

15. Level 2 Static Device Eqs. (cont.)
Mobility variation
KP’ =
KP*[(esi/eox)*UCRIT*TOX
/(vgs-VTH-UTRA*vds)]UEXP
This replaces KP in all other formulae.
©rlc L37-04May2011

16. SPICE Parameters Level 3
©rlc L37-04May2011

17. BJT Self-heating
Self heating of the transistor is proportional to the power dissipated.
Temperature Rise = ΔT = Rth ∙Power
The VBIC model was developed to simulate the BJT such that the device temperature tracked power dissipation in real time.
Other circuit simulators which accommodate thermal resistance are
HICUM
MEXTRAM
©rlc L37-04May2011

18. Rth Estimation for a Small Diode-isolated BJT Device
VBE=0.87 V and VCE=20 V, RTH = 341 C/W
©rlc L37-04May2011

19. VBIC Model Highlights Self-heating effects includeddt tl
Self-heating effects included
Improved Early effect modeling
Quasi-saturation modeling
Parasitic substrate transistor modeling
Parasitic fixed (oxide) capacitance modeling
An avalanche multiplication model included
Base current is decoupled from collector current
©rlc L37-04May2011

20. 2-D Isotherm Plot- Lines Connecting Points of Equal Temperature
2-D Isotherm plots for a structure scaled to be the same as the P10 1X2X1 device.
©rlc L37-04May2011

21. Thermal Model of a SiGe HBT
The structure of a typical SiGe HBT (Heterojunction Bipolar Transistor) [1]
The Electrical circuit topology (Cauer network) for the thermal analogy model
Oxide
©rlc L37-04May2011

22. One Dimensional Heat Flow in Silicon
AMBIENT
HEAT
SILICON
A silicon structure can be sub-divided into several silicon slabs.
Each section contributes to the total Rth and Cth of the structure. If each section is of equal volume, their individual Rth and Cth should be equal in value.
To correspond to uniform heat flow, each section can be represented by a thermal resistance and half the total capacitance on each node of the resistor.
Cth 2
Rth
©rlc L37-04May2011

23. The Distributed Nature of the Heat Flow
The corresponding CTh /2 capacitors are aggregated at each node.
Note that the “ambient end” CTh /2 is short-circuited.
The distributed equivalent circuit analogy simulation is obtained from the following network.
Rth n
Cth 2n
Add formula
Rth = Total Thermal resistance for the silicon structure
Cth= Total Thermal capacitance of the silicon structure
n = number of sections
A=area
cp= thermal capacitance
ρ=density
t= thickness
kp= thermal conductance
©rlc L37-04May2011

24. Comparison of Circuit Analogy to Davinci Simulation of the Heat Flow
Considering a silicon structure of size 3.7umx2.5um x10um
Dividing the structure into 10 sections.
where i=1,2,3…n,
n= number of sections
Dotted line=Davinci simulation measurement
Solid line = equivalent circuit simulation
©rlc L37-04May2011

25. Approximating the Distributed Circuit With a Single Pole Model
Converting the 10 element distributed model to a 1 pole model:
RTotal=Rth at ‘dc’
ΔQTotal =(cp)(ρ)Tavg
For total heat consumption.
Heat stored corresponds to charge stored for the equivalent circuit.
How the davinci simulation and parameter , rth total , cth total add slide for simulation using calculation. Parameter values of the circuit simulation.
Rth n
Cth 2n
©rlc L37-04May2011

26. Comparison of Circuit Analogy to Davinci Simulation for Heat Flow
©rlc L37-04May2011

27. (cont’d) Top of the tub Top of the oxide Top of the wafer
Results from equivalent circuit simulations
Results from Davinci Simulation
Results from device measurement Foster network
Results from device measurement Cauer network
Top of the tub
Top of the oxide
Top of the wafer
©rlc L37-04May2011

28. Circuit used for simulations
©rlc L37-04May2011

29. dt for VBIC-R1.5 model Model: VBIC-R1.5. “selft” flag set to 1.
No optimization done.
No external circuit connected.
Rth=5.8E+0
Cth=96E-12
©rlc L37-04May2011

30. VBIC-R1.5 Y11 plot (standard data)
©rlc L37-04May2011

31. VBIC-R1.5 Y11 plot (standard data)
©rlc L37-04May2011

32. VBIC-R1.2 Y11 plot (optimized data)
For optimized data refer slide “Model Parameters”.
Circuit used is shown in “Circuit for Y parameters (optimized data)” slide. fc Τ
fc1= 2E3
7.962E-05
fc2= 9.25E4
1.721E-06
fc3= 3.2E6
4.976E-08
Fc4=2E3
Fc5=1E5
1.592E-06
Fc6=4E6
3.981E-08
fc7= 2E3
fc8= 1E5
fc9=4E6
©rlc L37-04May2011

33. Spreadsheet for Calculating the Rth and Cth
Calculations mentioned in the previous slides have been implemented in an Excel spreadsheet.
The Cauer to Foster network transformation is done. 
The spreadsheet takes the dimensions of different layers of the devices and gives corresponding Cauer and Foster network values. This enables the calculation of time constants which can be converted into a single pole. The characteristic times for the Foster network appear on a impulse response plot.
Fig. 7. Electrical equivalent Cauer network of the HBT
Fig. 8. Electrical equivalent Foster network of the HBT
©rlc L37-04May2011

34. Effect of Rth on current feedback op-amp settling time+
vIN = 1 V P-P, t = 200 m-sec
500 W
vOUT
100 W
©rlc L37-04May2011

35. Current Feedback Op Amp Data (LMH6704) Switching Offset
©rlc L37-04May2011

36. LMH6550 impulse thermal characteristics
LeCroy sampling oscilloscope (1MW input mode)
Maximum averaging (10000)
Input nominally +/- 1V with 50 micro-sec period and 50% duty cycle.
Fractional Gain Error = FGE
©rlc L37-04May2011

37. vIN Rising Response
vIN
FGE
vOUT
©rlc L37-04May2011

38. vIN Falling Response
vOUT
FGE
vIN
©rlc L37-04May2011

39. Current Feedback Op-Amp (CFOA) with Simple Current Mirror (CM) Bias
sup
©rlc L37-04May2011

40. Large-signal Output Voltage Transient Analysis for CFOA with Simple CM Biasing
©rlc L37-04May2011

41. Hypothesis: The Thermal Tail is a Linear Superposition of the Contribution from each Individual Circuit Stick
The contribution of individual transistor to the total thermal tail.
Used six stick classifications according to transistor type and functionality.
i.e. Q10stk3-pnp-bf and Q11stk4-npn-cm
Enabled the self-heating effect in the stick of interest and disabled the self-heating effect of the remaining transistors.
Simulated the contribution of each individual stick.
The total thermal tail simulated is essentially the sum of the individual thermal tail contributions of each circuit stick.
©rlc L37-04May2011

42. The Hypothesis Supported
Area x1
Area x8
Thermal Tail (uV/V)
High-to-Low
Low-to-High
stk2-npn-bf (Q5)
-822
842
-124
128
stk2-pnp-bf (Q6)
-727
712
-101 98
stk2-npn-cm (Q2)
-89 91
-11 12
stk2-pnp-cm (Q4)
-91 89
-10 9
stk3-npn-bf (Q7)
-877
850
-111
106
stk3-pnp-bf (Q8)
-783
808
115
stk4-npn-cm (Q12)
-1213
1217
-172
173
stk4-pnp-cm (Q10)
-1075
1073
-159
158
stk5-npn-bf(Q13) 13
-13 2 -2
stk5-pnp-bf(Q14) -4 4 -1 1
stk5-npn-cm(Q18) 16
-15
stk5-pnp-cm(Q17) -5
stk6-npn-bf(Q15)
stk6-pnp-bf(Q16)
added total
-5658
5661
-796
796
simulated total
-5311
5313
-789
789
©rlc L37-04May2011

43. References
Fujiang Lin, et al, “Extraction Of VBIC Model for SiGe HBTs Made Easy by Going Through Gummel-Poon Model”, from
Avanti Star-spice User Manual, 04, 2001.
Affirma Spectre Circuit Simulator Device Model Equations
Zweidinger, D.T.; Fox, R.M., et al, “Equivalent circuit modeling of static substrate thermal coupling using VCVS representation”, Solid-State Circuits, IEEE Journal of , Volume: 2 Issue: 9 , Sept. 2002, Page(s):
©rlc L37-04May2011

44. Thermal Analogy References
[1] I.Z. Mitrovic , O. Buiu, S. Hall, D.M. Bagnall and P. Ashburn “Review of SiGe HBTs on SOI”, Solid State Electronics, Sept. 2005, Vol. 49, pp [2] Masana, F. N., “A New Approach to the Dynamic Thermal Modeling of Semiconductor Packages”, Microelectron. Reliab., 41, 2001, pp. 901–912. [3] Richard C. Joy and E. S. Schlig, “Thermal Properties of Very Fast Transistors”, IEEE Trans. ED, ED-1 7. No. 8, August 1970, pp [4] Kevin Bastin, “Analysis and Modeling of self heating in SiGe HBTs” , Aug. 2009, Masters Thesis, UTA. [5] Rinaldi, N., “On the Modeling of the Transient Thermal Behavior of Semiconductor Devices”, IEEE Trans-ED, Volume: 48 , Issue: 12 , Dec. 2001; Pages:2796 – 2802.
©rlc L37-04May2011

45. Simulation … References
[1] E. Castro, S. Coco, A. Laudani, L. LO Nigro and G. Pollicino, “A New Tool For Bipolar Transistor Characterization Based on HICUM”, Communications to SIMAI Congress, ISSN , Vol. 2, 2007.
[2] K. Bastin, “Analysis And Modeling of Self Heating in Silicon Germanium Heterojunction Bipolar Transistors”, Thesis report, The University of Texas at Arlington, August 2009.
©rlc L37-04May2011

46. AICR Team at University of Texas Arlington - Electrical Engineering
Current
Earlier Contributors
Ronald L. Carter, Professor
W. Alan Davis, Associate Professor
Howard T. Russell, Senior Lecturer
Ardasheir Rahman1
Xuesong Xie3
Arun Thomas-Karingada2
Sharath Patil2
Valay Shah2
Kevin Bastin, MS
Abhijit Chaugule, MS
Daewoo Kim, PhD
Anurag Lakhlani, MS
Zheng Li, PhD
Kamal Sinha, PhD
1PhD Student
2MS Student
3Post-doctoral Associate
©rlc L37-04May2011

47. References
CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995.
M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993.
**M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986.
*Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997
©rlc L37-04May2011