# Semiconductor Device Modeling and Characterization – EE5342 Lecture 35 – Spring 2011 Professor Ronald L. Carter

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Semiconductor Device Modeling and Characterization – EE5342 Lecture 35 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

©rlc L35-29Apr2011 Flat-band parameters for p-channel (n-subst)

©rlc L35-29Apr2011 Fully biased p- channel V T calc

©rlc L35-29Apr2011 p-channel V T for V C = V B = 0 Fig 10.21*

Mobilities

©rlc L35-29Apr2011 Differential charges for low and high freq From Fig 10.27* high freq.

©rlc L35-29Apr2011 Ideal low-freq C-V relationship Fig 10.25*

©rlc L35-29Apr2011 Comparison of low and high freq C-V Fig 10.28*

©rlc L35-29Apr2011 Effect of Q’ ss on the C-V relationship Fig 10.29*

©rlc L35-29Apr2011 n-channel enhancement MOSFET in ohmic region 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat e - e - e - e - e - n+ p-substrate Channel

©rlc L35-29Apr2011 Conductance of inverted channel Q’ n = - C’ Ox (V GC -V T ) n’ s = C’ Ox (V GC -V T )/q, (# inv elect/cm 2 ) The conductivity  n = (n’ s /t) q  n G =  n (Wt/L) = n’ s q  n (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’ s q  n W)

©rlc L35-29Apr2011 Basic I-V relation for MOS channel

©rlc L35-29Apr2011 I-V relation for n-MOS (ohmic reg) IDID V DS V DS,sat I D,sat ohmic non-physical saturated

©rlc L35-29Apr2011 Universal drain characteristic 9I D1 IDID 4I D1 I D1 V GS =V T +1V V GS =V T +2V V GS =V T +3V V DS saturated, V DS >V GS -V T ohmic

©rlc L35-29Apr2011 Characterizing the n-ch MOSFET VDVD IDID D S G B V GS VTVT

©rlc L35-29Apr2011 Low field ohmic characteristics

©rlc L35-29Apr2011 MOSFET Device Structre Fig. 4-1, M&A*

©rlc L35-29Apr2011 Body effect data Fig 9.9**

©rlc L35-29Apr2011 MOSFET equivalent circuit elements Fig 10.51*

©rlc L35-29Apr2011 n-channel enh. circuit model G D B S C gs C gd C gb C bs C bd RD RG RB RDS Idrain D SS D SD

©rlc L35-29Apr2011 MOS small-signal equivalent circuit Fig 10.52*

©rlc L35-29Apr2011 MOSFET circuit parameters (cont)

©rlc L35-29Apr2011 Substrate bias effect on V T (body-effect)

©rlc L35-29Apr2011 Body effect data Fig 9.9**

©rlc L35-29Apr2011 Fully biased n- channel V T calc

©rlc L35-29Apr2011 Values for  ms with silicon gate

©rlc L35-29Apr2011 Q’ d,max and x d,max for biased MOS capacitor Fig 8.11** x d,max (microns) |Q’ d,max |/q (cm -2 )

©rlc L35-29Apr2011 I-V relation for n-MOS IDID V DS V DS,sat I D,sat ohmic non-physical saturated

©rlc L35-29Apr2011 MOS channel- length modulation Fig 11.5*

©rlc L35-29Apr2011 Analysis of channel length modulation

©rlc L35-29Apr2011 References CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995. M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993. **M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986. *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997

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