1. General Overview of Modelling and Test Methodology of HV MOSFET J Rhayem, B Desoete, S. Frere, R. Gillon AMIS Semiconductor Belgium BVBA Westerring 15, B-9700 Oudenaarde Belgium. www.amis.com

2. OUTLINE 1/ Modeling Flow : Silicon to Modelkit library 2/ AMIS Model Topology of HV MOSFET 3/ Correlation Corners 4/ Testing methodology

3. General Modelling Flow Data for Modelling Purpose (standard data and special data requested in the MRF*) Ex: for MOS 1/ IDVGS, GMVGS @ low VDS and different VBS 2/ IDVDS, GDVDS at different VGS 3/ Substrate Leakage 4/ Drain to Gate and Drain to Source capacitance versus VGS and VDS 5/ parasitic Junction capacitance 6/ junction leakage 7/ Low frequency noise 8/ VTH and Beta Mismatch Building up the model card as a sub circuit 1/ Model extraction of the main device ICCAP,UTMOST, Matlab, Perl customized routines are used for optimization purpose 2/ Adding models of the parasitic component 4/ Building up skew models (3 corners) 3/ Implementation of the SOA flags based on Reliability inputs 4/ Implementation of the matching parameter in the corresponding matching file Modelling frame on Test chip Ex: MOS WL arrays MOS matching RF frames Model Kit test Running basic and specific tests at device level (simulate a netlist) and at circuit level (simulation of schematic in Design Environment)

4. DMOS Cross section H At low current / gate voltage the channel controls the operation H At high current the drift region is saturated and forces the channel back into linear operation H Voltages across body / drain junction and thin gate-oxide region remain low, even at high drain voltage thanks to large voltage drop across the drift region. JFET or Bias dependent drift resistance

5. DC and AC DMOS Characteristics DMOS : TYPICAL OUTPUT CHARACTERISTICS I intrinsic MOS channel pinch-off II quasi-saturation + self-heating III quasi-saturation Gate to drain and gate to Source Capacitance Special Behaviour of Capacitance for HV DMOS

6. DMOS Model Topology Standard Models existing in software package cannot predict correctly all special effect seen in DMOS Need for a customized subcircuit

7. Methodology to Generate Corners Correlation analysis on ETEST Define Correlation Group Device types, Device Groups and/or device family Objective: Improved statistical modeling Univariate approach : reduced nb of corners PCA -> Multivariate approach Realistic Corners Transform ETETS parameter corners into model Parameter corners using trained Neural Network

8. Group of Correlated Realistic Corners

9. Generating Model Corners Principle Component Analysis (ex DMOS) : Multivariate Approach

10. Generating Model Corners Link between ETEST parameters and DMOS model parameters VTH GM max ID sat R on tox vth 0 u0 vsat R tox VTH Gm max ID sat R on tox Neural Network vth0 u0 vsat R tox Measurements Model Par. Vectors E-Test VectorsModel Par. Vectors Simulations Typical Model DOE Sensitivity Ranking E-Test Vectors Neural Network Training

11. HV MOS Model Features  Features of HV DMOS models –DC, AC and transient model –Scalability –Temperature –DC and AC corners –Parasitic components –Safe operating area included –VT and Beta mismatch coefficients Matching parameters

12. Testing the Model Kit Test at device level  Accuracy test :   corners and @ : -40C / +25C / +150C, –check average error between measured and simulated main electrical parameters : ex for MOS (VTH, BETA, GMMAX, IDSAT) for BJT (BETAMAX, VERALY, RCOL, BVCEO …), –Review Major Characteristics and accuracies (IDVD, IDVG, GM, GD …) for MOS, (Gummel Poon, Output characteristics) for BJTs –Absence of errors / warnings in simulation logs  Specific tests: Scalability, temperature check,

13. Testing the Model Kit Test At Circuit Level  Quality tests : Delay Chains at different temp, OpAmp DC, Trans and AC, Ring Oscillator, HS driver, Band Gap … MODELLING BUILD UP A LARGE TEST BENCH BASED ON THE REQUESTS SENT BY ANALOG DESIGNERS FOR CIRCUITS WHERE PROBLEMS APPEARED AND HAVE BEEN SOLVED MODELING USES THESE CIRCUITS WHEN RUNNING QUALITY TEST  Convergence tests  Deterministic matching tool  SOA :  Test a violation for each rule

14. Conclusion Review HV Modeling Methodology in AMIS HV Model Perspective:  Aging Model  Self Heating