1. Preliminary LumiCAL FEE Specification Presented by Alexander Solin NC PHEP solin@hep.by FCAL collaboration meeting, February 12-13, 2006, Krakow (INP PAS), Poland

2. February 12-13, 2006, Krakow A.Solin2 Contents  Preliminary LumiCAL FEE Specification  ASICs for FCAL detectors prototypes (main parameters measurement setup, bench and beam tests)

3. February 12-13, 2006, Krakow A.Solin3 Preliminary LumiCAL FEE Specification

4. February 12-13, 2006, Krakow A.Solin4 Estimation of the pad Si-sensor capacitancies

5. February 12-13, 2006, Krakow A.Solin5 Estimation of the strip Si-sensor capacitancies

6. February 12-13, 2006, Krakow A.Solin6 Estimation of the maximum Si-sensor charge collection (1-1000)MIP channel signal range from B.Pawlik’s talk

7. February 12-13, 2006, Krakow A.Solin7 LumiCal Si-sensor parameters MaterialSi Think,  500  si 11.8 Depletion voltage, V155 Collection charge time, ns28 MIP,e40000 Capacitance range calculation (look previous pictures ) Minimum valueMaximum value Pad option42pF295pF Strip option isolated concentric sectors28pF395pF bonded concentric strips168pF571pF

8. February 12-13, 2006, Krakow A.Solin8 LumiCAL ASIC requirements Signal to Noise Ratio (SNR)5 Maximum ENC, e8000 Maximum signal, MIP1000 Dynamic range, bit12-13 Shaping time, ns70 Amplitude output, V2 Gain, mV/fC0.31 Channel structure of the first prototypePreamplifier - Shaper Number of channels per chip (rough estimation) Detector mounting surface area, cm 2 3956 (for 22.5 cm detector length) Chip mounting surface area, cm 2 4 Total number of chips989 Number of channels per chip Pad option12 Strip option14 (4 in case of bonded concentric strips) Number of channels per chip fixed by tile size22 (cheap package), 44

9. February 12-13, 2006, Krakow A.Solin9 ASIC technologies Minsk1.5µ design rules Bi-JFET 0.8µ design rules CMOS 0.6µ design rules Bi-CMOS Leading European and Asiatic FABsup to deep submicron design rules (if it is reasonable) Next four pictures can help to estimate noises of frond end electronics. Calculations are done for Bi-JFET technology (see picture). Same calculations can be done for other technologies. Preamplifier noises will be similar to the presented calculations.

10. February 12-13, 2006, Krakow A.Solin10 Capacitance of Si-sensor vs its area 572pF 28pF

11. February 12-13, 2006, Krakow A.Solin11 ENC vs preamplifier power consumption 8000e

12. February 12-13, 2006, Krakow A.Solin12 ENC vs shaping time 8000e

13. February 12-13, 2006, Krakow A.Solin13 ENC vs Si-sensor Capacitance 572pF

14. February 12-13, 2006, Krakow A.Solin14 ASICs for FCAL detectors prototypes (main parameters measurement setup, bench and beam tests)

15. February 12-13, 2006, Krakow A.Solin15 Tetrode-BT, Tetrode-JFET ASICs 1996 year, CMS ECAL Two designs CSP were made in Minsk NC PHEP with slightly different circuits for amplifying of signals from Hamamtsu R2149 vacuum phototetrode: “TETRODE-BT” with bipolar input transistor; “TETRODE-JFET” with p-JFET input transistor.

16. February 12-13, 2006, Krakow A.Solin16 Design requirements to Tetrode CSPs Hamamtsu R2149 parameters: CSP requirements: Ca15pF Anode dark current0.1 nA Typical gain (HV= -900V, B= 0 T)30 Quantum eff. at 500 nm10% ENC, e<1000 Dynamic range, bit13 Output signal width (base-to-base), ns100ns

17. February 12-13, 2006, Krakow A.Solin17 CSP based on Tetrode JFET ENC=320e+18e/pF, Tp=800ns

18. February 12-13, 2006, Krakow A.Solin18 AS01PDA, AS01T ASICs 2002 year, TESLA THCAL Next AS01PDA ASIC were designed and manufactured in Minsk NC PHEP for amplifying of signals from photodetectors. The AS01PDA ASIC is a development of the “Tetrode BT” design line. It additionally contains a shaper and shaper gain control stage.

19. February 12-13, 2006, Krakow A.Solin19 AS01PDA main parameters Number of channels1 Circuit structurePreamplifier + Shaper + 50 Ohm Driver Additional propertyShaper Gain Control Shaper peaking time90ns Max. Gain9mV/fC ENC, e1000+14.1e/pF Shaper output+/-1.5V Power consumption18mW PackageSOP16

20. February 12-13, 2006, Krakow A.Solin20 AS01PDA block diagram

21. February 12-13, 2006, Krakow A.Solin21 AS01PDA tests  October, 2002  Output signals were digitalized with theTDS3032 scope.

22. February 12-13, 2006, Krakow A.Solin22 AS01PDA noise curves  February, 2006  Noise is measured with the Infiniium 54830B scope.

23. February 12-13, 2006, Krakow A.Solin23 ASIC for large capacitance detectors AS01T is optimazed for using with large capacitance detectors.  It has the same structure as AS01PDA.  The package is the same too.  Both chips (AS01T and AS01PDA) are placed on the same wafer and are manufactured in one process.

24. February 12-13, 2006, Krakow A.Solin24 Conclusion The next steps of development of FEE for FCAL  Making of readout electronics for immediate beam tests (Tetrode, AS01 ASICs)  Qualification of LumiCAL ASIC specification and design of new prototype of 22 channel preamplifier-shaper ASIC for amplifying of Si-detector signals.  Creation of multichannel readout electronics for larger FCAL prototypes.