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Electronics for large LAr TPC’s F. Pietropaolo (ICARUS Collaboration) CRYODET Workshop LNGS, 13-14 March 2006.

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Presentation on theme: "Electronics for large LAr TPC’s F. Pietropaolo (ICARUS Collaboration) CRYODET Workshop LNGS, 13-14 March 2006."— Presentation transcript:

1 Electronics for large LAr TPC’s F. Pietropaolo (ICARUS Collaboration) CRYODET Workshop LNGS, March 2006

2 13-14 March 2006CryoDet workshop, LNGS 2 Outline The ICARUS front-end electronics Layout in T600 module (analogue + digital) Performance and limitations Possible upgrades for multi-kton detectors Alternatives solutions Front-end inside vs outside LAr Analog-to-digital serial converter Summary

3 13-14 March 2006CryoDet workshop, LNGS 3 The ICARUS T600 experience The T600 DAQ system (5·10 4 channels), designed in Padova, engineered and built by CAEN, has proven to perform satisfactory during the 2001 test run in Pavia. It consists of an analogue front-end followed by a multiplexed AD converter (10 bit) and by a digital VME module performing local storage, hit finding and data compression. From the experience gained with the T600 operation, an R&D phase is underway in view of an upgrade for a multi-kton detector with ~ n·10 5 channels (better S/N, larger integration, lower cost).

4 13-14 March 2006CryoDet workshop, LNGS 4 The ICARUS read-out principle Time Drift direction Mux Hit finder multi-event circular buffer E drift ~ 500 V/cm To storage m.i.p. ionization ~ 6000 e - /mm FADC Memory 8:1 400ns Daedalus n x 4kB Low-noise amplifiers Front-end Continuous waveform recording

5 13-14 March 2006CryoDet workshop, LNGS 5 The induction signals ICARUS T600: three wire planes (pitch 3mm, separation 3mm) d d p Electrons path Drift Ionizing track T=0 Induced current Induced charge u-t view v-t view w-t view E drift E2E2 E1E1 Drift time E drift = 500 V/cm Mip signal ~ e - (inc. recombinantion) Electron drift velocity ~ 1.5 mm/  s Typical grid transit time ~ 2-3  s Induction 1 Induction 2 Collection Charge = area Charge = ampl.

6 13-14 March 2006CryoDet workshop, LNGS 6 Requirements for the preamplifier Need of very low noise amplifier: No amplification around sense wires Induced charge ~ 10 4 electrons Large input capacitance (C D ) Wires (20 pF/m) + cables (50 pF/m) In T600 C D ~ pF Serial noise (proportional to C D ) dominates over parallel noise (proportional only to signal bandwidth) High trans-conductance (g m ) input device required to ensure acceptable Signal-to Noise level (S/N ~ 10)

7 13-14 March 2006CryoDet workshop, LNGS 7 Choice of the active input device Bipolar transistors g m ≈ I c ≈ 10 mA (Amplification merit factor g m ·Z out ≈ 3-4·10 5 ) BUT: parallel noise density ≈ 2 pA / √Hz too high (with a typical LAr signal bandwidth of ~ 1 MHz gives unacceptable noise contribution) VLSI-CMOS Extremely low g m jFET Good g m ≈ I ds ≈ 10 mA (Amplification merit factor g m ·Z out ≈ 3-4·10 4 ) negligible parallel noise density ≈ pA / √Hz ICARUS choice since 1986: charge sensitive preamplifier with high g m jFET input stage

8 13-14 March 2006CryoDet workshop, LNGS 8 The ICARUS T600 preamplifier Custom IC in BiCMOS technology Classical Radeka integrator External input stage jFET’s Two IF4500 (Interfet) or BF861/2/3 (Philips) in parallel to increase g m (50-60 mS) External feed-back network Allow sensitivity and decay time optimization High value f.b. resistor (100M  ) reduce parallel noise External baseline restorer circuit Two channels per IC Identical symmetrical layout guarantees identical electrical behavior Sensitivity ≈ 6 mV/fC Dynamic range > 200 fC Linearity < full scale Gain uniformity < 3% E.N.C. ≈ ( x C D ) el ≈ pF Power consumption ≈ 40 mW Two versions: “quasi-current” mode: R f C f ≈ 1.6  s (collection + first induction) “quasi-charge” mode: R f C f ≈ 30  s (mid induction)

9 13-14 March 2006CryoDet workshop, LNGS 9 Layout of front-end electronics Twisted pair cables (~5m, 50pF/m) Liquid argon Gas Decoupling Boards (32 ch.) UHV Feed-through (18x32ch.) Front-end amplifiers (32/board) Sense wires (4-9m, 20pF/m) H.V. (<±500 V) VME board (18/crate) 4 Multiplexers (400ns x 8ch.) 10bit FADC 400ns sampling 1mV/ADC ICARUS T600: ~ channels — 1720 boards — 96 crates Cost of the full electronic chain: ~ 80 € / channel

10 13-14 March 2006CryoDet workshop, LNGS 10 The ICARUS T600 read-out chain CAEN-V789 board: 2 Daedalus VLSI * 16 input channels (local self-trigger & zero suppression) + memory buffers + data out on VME bus CAEN-V791 board: 32 pre-amplifiers + 4 multiplexers (8:1) + 4 FADC’s (10 bits - 20 MHz) Decoupling board: HV distribution and signal input Signal UHV feed-through: 576 channels (18 connectors x 32) + HV wire biasing

11 13-14 March 2006CryoDet workshop, LNGS 11 The T600 electronic racks

12 13-14 March 2006CryoDet workshop, LNGS 12 The analogue board V791 BiCMOS IC layout Multiplexers FADC’s Preamplifiers Shielding of front-end Digital link Output of analogue sum Input signal connector

13 13-14 March 2006CryoDet workshop, LNGS 13 Performance of the V791 boards V791C V791Q Collection 1 st Induction Mid. Induction 128 wires/view 1024 samples 400 ns/sample

14 13-14 March 2006CryoDet workshop, LNGS 14 Performance of the V791C board RMS noise on T600 = ADC counts (due to difficult environment in Pavia) Single wire waveforms (horiz. axis unit = 400 ns) Collection 1 st Induction Test pulse (6 mm m.i.p) 24 ADC counts FWHM ≈ 5 µs Noise RMS ≈ 1.3 ADC counts Coherent noise due to layout not negligible! m.i.p. ≈ 12 ADC counts (3 mm) FWHM ≈ 5 µs

15 13-14 March 2006CryoDet workshop, LNGS 15 Single wire waveforms (horiz. axis unit = 400 ns) Performance of the V791Q board Pulse height & shape from mid. plane wires very similar to those from collection plane wires. High frequency S/N also comparable. Low frequency minimized by baseline restorer. Test pulse (6 mm m.i.p.) 24 ADC counts RC ≈ 30 µs Noise RMS (h.f.) ≈ 1.2 ADC counts Low frequency noise visible but not dangerous! m.i.p. ≈ 10 ADC counts (3 mm) FWHM ≈ 5 µs Mid. Induction

16 13-14 March 2006CryoDet workshop, LNGS 16 Events from T300 semi module Collection view Induction2 view Drift time (1.5m) Wire numbering (4.5m) Drift time (1.5m) Wire numbering (4.5m)

17 13-14 March 2006CryoDet workshop, LNGS 17 Possible upgrades In a multi-kton LAr-TPC with the ICARUS read-out principle we can foresee S/N close to T600 Longer electrodes (larger input capacitance, more electronic noise) But probably larger electrode pitch (more input charge) Larger number of channels (~ n10 5 ) Require integration, cost reduction Present overall architecture fully satisfactory Improvement will focus on Input stage jFET Technology still state of the art Optimization of number of input jFET to larger input capacitance Review IC design - Integrate more channels BiCMOS technology evolved since last IC design Careful study of layout topology Development of new hybrid sub module Hosting more amplification channels (e.g ) And, possibly, the analogue-to-digital converter stage

18 13-14 March 2006CryoDet workshop, LNGS 18 Electronics in LAr Deeply investigated within ICARUS collaboration (since 1988) Limited choice of active devices working at LAr temperature GAs-jFET (High Electron Mobility Transistor technology) Silicon jFET (High Resistive Substrate technology) Expected characteristics: Better S/N due to improved g m at cryogenic temperature Reliability at LAr temperature Availability on the market Carrier mobility decrease Pinch-off increase U310 jFET

19 13-14 March 2006CryoDet workshop, LNGS 19 Pro & Contra Advantages Reduction of input capacitance due to cable absence Reduction of micro-phonic noise (detector = Faraday cage) Intrinsic improvement of S/N due to larger jFET g m at cryogenic temperature Disadvantages Inaccessibility during detector operation Need of careful selection of components, extensive burn-in and temperature cycles before installation to minimize components failure Design architecture and technology restricted by limited choice of active components Limit on power dissipation (< 100 mW/mm 2 to avoid LAr boil-off)

20 13-14 March 2006CryoDet workshop, LNGS 20 The TOTEM architecture Charge Integrator made on Thick Film Hybrid technology with discrete jFET only Minimum active and passive components Ability to drive long transmission line Reduced power consumption Minimum cable connections Current signal from Positive Power Supply Common Negative polarization Characteristics Optimized for low detector capacitance Sensitivity ≈ 0.45 mV/fC (0.9  A/fC) Dynamic range ±1.5 pC Linearity < full scale Input impedance ≈ 420  Input capacitance ≈ 20 pF E.N.C. ≈ ( x C D ) el Power consumption ≈ 11 mW (IF1330)

21 13-14 March 2006CryoDet workshop, LNGS 21 Events with electronics in LAr Extensively used on the 50 liter LAr-TPC Wire capacitance: ~ 15 pF Collection Noise RMS ≈ 0.7 ADC counts Negligible low frequency noise ! mip ≈ 10 ADC counts (2.54 mm) FWHM ≈ 6 µs (horiz. axis unit = 400 ns) Collection Induction

22 13-14 March 2006CryoDet workshop, LNGS 22 The ICARUS experience Electronics in LAr studied for sake of completeness Not a viable solution for large scale detectors Inaccessibility, poor integration, cost However TOTEM design could be improved HEMT replacing silicon jFET jFET matrix on single chip Technology commercially available for low temperature application E.g. INTERFET IPA300 amplifier (serial noise density = 0.6 nV / √Hz, 80 mW dissipation)

23 13-14 March 2006CryoDet workshop, LNGS 23 Analog-to-digital conversion Present architecture Serves sets of 16 channels through analogue multiplexers and 10 bit FADC’s Trade-off between sampling speed and price FADC sampling rate 20MHz interleaved 400 ns sampling time / channel 40MHz digital output Dissipated power ~ 500 mW Components cost ~40 € / 16 channels Two sets per V789 board (32 ch.) Total bandwidth = 800 Mbit/s

24 13-14 March 2006CryoDet workshop, LNGS 24 Compact serial AD converter New architecture based on 1-bit serial converter Interesting characteristics No need for multiplexing Very low number of components Resolution better than 10 bit Commercially available chip Low price (< 1 € / channel) Basic structure Four QUAD FLATPACK 4x4 mm 2 components plus few glue logic Sampling rate = 16 MHz Dissipated power = 400mW Data reconstruction Simple FIR filters could be implemented In pipeline on FPGA / DSP Off line after data storage Serving multiples of 16 channels Test underway of 16 channel prototype boards fully compatible with present ICARUS data link Total bandwidth = 256 Mbit/s Upgradable to 800 Mbit/s if sampling rate increased to 25 MHz and 32 channels

25 13-14 March 2006CryoDet workshop, LNGS 25 Serial ADC frequency response 16 MHz 25 MHz 16 sample FIR comb filter equivalent to 10 bit resolution Typical ICARUS signal bandwidth (~ 1 MHz) better matched in 25 MHz case. Marginal in the 16 MHZ case 8 sample FIR comb filter equivalent to 8 bit resolution

26 13-14 March 2006CryoDet workshop, LNGS 26 Simulations Typical ICARUS signal waveform (~3  s width) digitized with Serial AD converter FIR comb filter applied to recover signal shape (16 sample width) 10 bit equivalent resolution 1 bit quantization noise Continuous reconstruction (useful feature for signal analysis) 16 MHz 25 MHz Input waveform Continuous reconstruction 400ns sampled (cfr. FADC) Slight pulse height reduction but area (= charge) unchanged

27 13-14 March 2006CryoDet workshop, LNGS 27 Signals from LAr 16 MHz 25 MHz Input waveform Continuous reconstruction 400ns sampling LAr signal waveforms (from oscilloscope) digitized with Serial AD converter simulator FIR comb filter applied to recover signal shape (16 sample width) Quantization noise well within analogue noise level

28 13-14 March 2006CryoDet workshop, LNGS 28 Prototype board 16 channels 16 MHz sampling rate Data link compatible with ICARUS DAQ Effective throughput 256 Mbit/s Digital link Charge sensitive preamplifiers 4 x 4 channel serial AD converters

29 13-14 March 2006CryoDet workshop, LNGS 29 First signals from prototype Test pulse injected on on-board preamplifiers Digitized signal recorded with ICARUS DAQ Off-line signal reconstruction with FIR comb filter (16 sample width) 16 MHz Input waveform Continuous reconstruction 400ns sampling High preamp. noise due to present board layout (analogue/digital interference) Zoom of gray shaded area

30 13-14 March 2006CryoDet workshop, LNGS 30 Summary The ICARUS R&D on electronics for large LAr-TPC’s Upgrade of the analogue front-end VLSI-CMOS technology for high channel integration excluded by simple S/N requirements Review of amplifier IC design could allow integrating more than two channel per chip Use of HEMT at input could help improving S/N Possible alternative solution Development of a completely new cold amplifier (hybrid based on TOTEM structure with jFET matrix or HEMT) for better S/N Major drawback: inaccessibility, component reliability, cost Upgrade of Analogue-to-digital conversion Serial-converter: promising alternative to Multiplexer + Flash ACD Intrinsically simpler,more compact, cheaper Comparable bandwidth and signal resolution Review of the data link with digital buffers Study the recent optical link development at LHC experiments to help defining a suitable solution for the LAr-TPC environment


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