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E. Atkin, E. Malankin, V. Shumikhin NRNU MEPhI, Moscow 1.

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Presentation on theme: "E. Atkin, E. Malankin, V. Shumikhin NRNU MEPhI, Moscow 1."— Presentation transcript:

1 E. Atkin, E. Malankin, V. Shumikhin NRNU MEPhI, Moscow 1

2  GEM  Chip structure  Channels structure  Test benches  Experimental data  Summary 2

3 Cross-section of a triple GEM detector 3 P. Abbon et al. / NIM (2007) 455–518 ~50 µm

4 Muon system of the international CBM experiment, being designed on the new accelerator facilities at FAIR GSI (Darmstadt, Germany), built on the base of the gaseous detector of high resolution. Muon System consists of about 1 million channels. For the Muon System signals read-out ASIC application is neccesary. 4

5 5

6 ~1 million channels ↓ ~ ASICs x 64 ch. 6

7 Muon system of the international CBM experiment, being designed on the new accelerator facilities at FAIR GSI (Darmstadt, Germany), built on the base of the gaseous detector of high resolution. Muon System consists of about 1 million channels. For the Muon System signals read-out ASIC application is neccesary. ~1 million channels ↓ ~ ASICs x 64 ch. Front-end for MUCH 7

8  Input signal range of fC  Charge polarity – negative  ENC – less than 0.3 fC  Detector capacitance up to 100 pF  Maximum hit rate/channel – 2 MHz  Power consumption – 2 mW/ch 8

9 1.5 CSA + stand alone Shaper channels (Preamp ver. 1) 2.5 CSA channel with built-in shaping (Preamp ver. 2) 3.OpAmp block 4.Digital test structures 9

10 10

11 Input transistor – nMOS (7mm * 360 nm) Common source stage Folded boost current amplifier Output source follower Feedback: gain setting cap + discharge transistor to set the maximum hit rate of channel not less than 2 MHz 11

12 Noninverting 2 nd order Sallen-Key filter The shaper has two additional adjustments: - TAIL – tail cancellation - SH_BL – baseline tuning 12

13 Input transistor – nMOS (4mm * 360 nm) Common source stage Folded boost current amplifier Output source follower Feedback: gain setting cap + discharge resistor to set the maximum hit rate of channel not less than 2 MHz 13

14 CLCC68 Package Die–1525 x 1525 μm 2 UMC 180 nm CMOS MMRF process 2012 run of Europractice 14

15 15 CLCC Socket LDO regulator 1 pF capacitance Detector capacitance emulation

16 16 CLCC Socket LDO regulator 1 pF capacitance Detector capacitance emulation Reference potentiometers

17 Input charge swept from 25 to 70 fC CSACSA & Shaper Shaper CSA Voltage pulser 17

18 Dynamic range – 1.5 – 100 fC Integral nolinearity ~ 4% Shaper Channel gain ~ 6 mV/fC CSA CSA gain ~ 2.5 mV/fC 18

19 Aim: C in >> C det Estimation: CSA open-loop gain ≥

20 transfer function CSA gain ~ 5 mV/fC CSA output 20

21 PreAmp (ver. 1) ENC – 875е Cdet = 1p 2427e Cdet = 100p PreAmp (ver. 2) ENC – 1070е Cdet = 1p 2500e Cdet = 100p 21

22 22 Socket with Chip GEM Anode Pad area 5x5 mm 2 Pad capacitance 12 pF Gas chamber with Ar/CO 2 *Testboard designed by PNPI team

23 55 Fe amplitude spectrum, obtained by the preamplifier & GEM. 23 *tests provided by PNPI team Preamplifier output

24 24 Designed and prototyped 2 versions of read-out with preliminary CBM MUCH specifications: Preamplifier (ver.1)Preamplifier (ver. 2) Gain6 mV/fC;5 mV/fC Input signal range fC; Maximum channel rate 2 MHz Power consumption1.2 mW/channel2 mW/channel ENC Cdet = 1p Cdet = 100p 875е 2427e 1070е 2500e Area on chip1050 x 100 µm200 x 100 µm

25 THANKS FOR YOUR ATTENTION... 25


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