3 Major Lithography Changes from 1999 ITRS Technology Node Timing accelerated 1-2 years130nm in 2001100nm in 2003 90nm in 2004MPU half-pitch accelerated one additional year.... now lags DRAM half-pitch by only one yearMPU gate length (in resist) set at 70% of DRAM half-pitch …. more aggressive than ORTCMPU physical gate length (post-etch) leads MPU gate length (in resist) by one yearNew DRAM chip sizes allow smaller minimum field size and 5X option for advanced optical toolsMEF drives much tighter optical mask requirementsChanges supported by 3 of 5 regions
4 ITRS Roadmap Acceleration (2000) 9597990205081114500199435025019971801998 & 1999Minimum Feature Size (nm)Half Pitch(IRC Proposals 7/11/00)13010070MPU Gate Length(printed in resist)50(post-etch)(IRC Proposals 7/11/00)35259597990205081114Proposed 2000 ITRS Update - 7/21/00Work-in-Progress - Not for Publication
5 Key Concerns for 2000 ITRS Update 1) Review of technology node timing2) SOC definition3) ROI study (model)4) SOC and MPU chip sizes5) Technical issues- Scanner reduction ratio- Mask (MEF)- Defect6) New devices - requirements, etc.
6 2000 ITRS Technology Node Timing Roadmap timing continues to be one of the major concerns for Lithography ITWGDiscussed extensively by all 5 regions at April and July ITWG meetings. Industry surveys conducted in Japan and USA.Consensus was not reached at July ITRS workshopThree proposals made since July meeting:#1 – IRC ORTC Revision 1 ke, 7/28/00#2 – USA Lithography TWG, 9/1/00#3 – Japan Lithography TWG, 9/28/00Two regions voted for proposal #2, one for proposal #3, and two abstainedLithography Requirements are based on proposal #2
7 2000 ITRS Chip & Field SizeHigh performance (HP) MPU drove minimum field size in 1999 Roadmap (>800mm2 at 50nm node)Chip Size Study Group (CSSG) reviewed models and current chips in this market segmentRecommended changing model to cut on-chip cache in half (1M in 1999 and doubling every 2 years)HP MPU chip size at 35nm node is now ~ 600mm2MPU designs can be very flexible, will be driven by economics, and should not be used to drive scanner field sizesCSSG also recommended that scanner field sizes should be driven by DRAM production chips/field
8 2000 ITRS Chip & Field SizeFEP ITWG studied issues with DRAM model, ‘a’ factor is too aggressiveAnalyzed tradeoffs of chip size growth rates, density increase rates, ‘a’ factor, and scanner field sizes 4X, and 5X on 6-inch glass)Final results show that 2 production chips can be contained in 572mm2 field sizeIRC agreed with FEP ITWG and CSSG recommendations and included in ORTCLithography TWG recommends staying at 6-inch glass for now and studying productivity benefits of 7-inch glass in the future
9 Scanner Reduction Ratio (SRR) ITWG recommends following issues be addressed at May 8, 2000 SRR Workshop organized by ISMT1) What is the timing? Node, year, wavelength?2) Comprehensive cost analysis- Impact of throughput reduction- Impact on mask industry; what real benefit do they get?- Does it help accelerate the Roadmap?3) Complications of 4X, 5X/6X on leading edge mask making?4) Do all scanner suppliers have to agree? What if they don’t?5) Impact on NGL? Must they follow? Especially EPL?
10 Scanner Reduction Ratio (SRR) Workshop May 8, 2000 The 62 attendees represented a broad cross-section of the industryVoting restricted to one response per company representedOne exception is allowed; “captive mask manufacturers” are asked to vote separately from their respective wafer linesChip ManufacturersMask Manufacturers
11 Mask Availability by Magnification Participants believed that the 70nm node mask availability could be improved by 2+ years if magnification increased above 4X
12 Optical Reticle Size Choice - 157nm 100nm Node - 157nmStay at 6”Minimal support for larger reticlesMore support for 7” than 9”Introduce 157nm with 5XSecondary choice mixed6X has more votes than 4X302520151054X 6"5X 6"6X 6"5X 7"6X 7"5X 9"6X 9"No 2ndChoice70nm Node - 157nm302520151054X 6"5X 6"6X 6"5X 7"6X 7"5X 9"6X 9"No 2ndChoice
13 Recommendations of Tool Suppliers (157nm Technology, Updated 11/9/00) Primary SecondaryASML 5X 6”Canon 5X 6”Nikon 4X 6” (5X 6”) *SVGL 4X 6”* However: If reticle accuracy can not be satisfied in the future, Nikon accepts changing to 5X for 157nm under the conditions of….Accepting lower throughput.Firmly standardizing optical reduction ratio.Accepting difficulties in mix & match between 4X & 5X.
14 Does NGL need to follow the magnification ratio of the optical tools?
15 SRR Workshop (5/8/00) Summary The majority choice for 157nm & 70nm node:Mask magnification 5XSlit height 22mmSubstrate 6-inchRecommend adding 5X as an option at 100nm & 70nm nodes for optical tools
16 Mask Error Factor (MEF) and Specifications Mask Error Factor (MEF) is the relation between changes in the pattern found on the mask and the corresponding pattern on the wafer:where M is the scanner reduction ratioIdeally MEF = 1.0. In practice, process variables can significantly increase the MEF as the image fidelity of the scanner deteriorates.Proposals organized through ISMT Optical Extensions & MASC groups in June meetings CD wafer (CD reticle) / MMEF =
17 Mask Error Factor (MEF) and Specifications ISMT contracted with IMEC to study MEF (modeling vs. experimental)Results show MEF increases very rapidly at duty ratio below 1:1.5; alternating PSM technology does NOT solve this issueMask specifications for dense lines must be much tighter (The 1999 relaxation was shown to be unwarranted)Recommend same CD uniformity specification for alternating PSM as for binary mask; requires more study in 2001
19 Lithography Requirements Exposure Tools - Table 39Continuous improvements in 248nm tools and processes have demonstrated solutions for DRAM and MPU down to 150nm half pitch, including CD control of 10nmMFS for development has been demonstrated down to 70nm with 193nm + PSMCD control solutions are being pursued down to 6nm by engineering analysis of error sources (mask, process, tool)Resists - Table 40Resist thickness solutions now exist down to umPEB solutions exist at 3nm / ºC with 248nm resistsResist sensitivity solutions exist for all resists except 157nm; solutions are being pursued at MIT/LL and suppliers for 157nm at 5-10 mJ/cm2Masks - Table 41Based on development of 50KeV e-beam writers, solutions now exist for mask minimum image size and OPC feature size to 200nm, image placement to 27nm, CD uniformity to 15nm, and linearity to 20nmCD uniformity for dense lines with alternating PSM must be much tighter due to better understanding of MEF
20 Lithography Requirements - Overview Solution Exists Solution Being Pursued No Known SolutionProposed 2000 ITRS Update - 10/14/00Work-in-Progress - Not for Publication
21 Lithography Exposure Tool Potential Solutions First Year of IC Production199920012004200720102013180248nm248nm + PSM193nm130193nm + PSM157nmEPLXRLIPLNarrowOptions90DRAM Half Pitch(Dense Lines)157nm + PSMEPLEUVIPLXRLEBDWTechnology Options at Technology Nodes (DRAM Half Pitch, nm)65NarrowOptionsEUVEPLIPLEBDWNarrowOptions45EUVEPLIPLEBDWINNOVATIVE TECHNOLOGYNarrowOptions33Research RequiredDevelopment UnderwayQualification/Pre-ProductionThis legend indicates the time during which research, development, and qualification/pre-production should be taking place for the technology solution.Note: Production level exposure tools should be available one year before first IC shipment.Proposed 2000 ITRS Update - 10/14/00 - Work-in-Progress - Not for Publication21
22 Key Challenges for Lithography in ITRS 2000 Update Impact of the technology node acceleration on lithography exposure technology and mask making capability.Gate CD control and overlay improvements.Ever tightening mask requirements, especially CD uniformity and image placement.Return on investment (ROI) for lithography suppliers, especially for single node solutions below 90nm.
24 Cost of Ownership Consider two comparison cases 157nm and EPL (Scalpel) at the 70nm nodeEUV and EPL (Scalpel) at the 50nm nodeCompare both at mask usage's of 500 and 5000 wpmISMT Dec.’99 - Rev. 4 assumptions (e.g. 25 x 25, 3rd yr, etc.)Analyze Cost of Ownership as a function of tool and mask cost “Mark-Up’s”
25 Cost of Ownership @ 70nm Node 50100150200250300350123456Cost Markup "X" (markup factor to both exposure tool and mask)Cost of Ownership ($/GWLE)157nm wpm157nm wpmEPL wpmEPL wpm
26 Cost of Ownership @ 50nm Node 50100150200250300350123456Cost Markup "X" (markup factor to both exposure tool and mask)Cost of Ownership ($/GWLE)EPL wpmEPL wpmEUV wpmEUV wpm
27 Cost ConclusionsTotal R&D spending for one regional solution could approach one billion dollars in 2002 aloneAlmost 2X previous spending ratesFinding both the funds and the necessary talented people may be biggest challenge of allRoadmap acceleration exacerbates business situation fewer tools, more improvements over shorter timeTo make sufficient ROI suppliers may have to increase mark-upIncreased tool and mask costs will drive up CoO at all mask usage levels
28 Lithography ITWG Report – 2000 Update Summary Technology Node Timing accelerated 1-2 years130nm in 2001 90nm in 2004Not a consensus decisionPuts major strain on entire lithography infrastructureNew DRAM and MPU chip sizes allow smaller minimum field size and 5X option for advanced optical tools with 6-inch reticlesOptical mask requirements for dense lines must be much tighter, based on latest MEF dataCost control and ROI continue to be major concerns for acceleration at 90nm – 45nm nodes
29 Lithography ITWG Report AcknowledgementsWe would like to express our most sincere gratitude and appreciation for the outstanding support and cooperation from the ITWG participants.Europe Paolo CanestrariJan-Willem GemminkJapan Hiroshi OhtsukaMasaru SasagoKorea Ki Ho BaikJoo-Tae MoonTaiwan Y.C. KuAnthony YenUSA George GombaGil Shelden