1. WP2 Review Meeting Milan, October 05, 2011 MODERN ENIAC WP2 Meeting (WP2-T2.4) WP2 and Tasks review Milano Agrate, 2011 Oct. 05 Meeting hosted by Micron

2. Relation among Work Packages 2WP2 Review Meeting Milan, October 05, 2011

3. T2.4 Task (1/2) Task T2.4: Correlation between PV and reliability, reliability modeling The impact of process variability on existing device reliability degradation models will be clarified. Aging measure-ments will be performed on test structures: Device degradation mechanisms will be identified based on silicon, their effect on PV parameters will be characterized and modeled to allow for a better description of aging during operation. Partners: AMS, IMEP, UNET, TUW, UNCA, UNGL UNGL will develop methodologies for the simulation of the statistical impact of NBTI and hot carrier degradation on the MOSFET characteristics in concert with the statistical variability sources described in T2.2 and its capture in statistical compact models. UNCA will perform aging measurements on nano-MOSFET devices focusing on the three main reliability mechanisms: hot- carrier injection, bias-temperature instability and time-dependent dielectric breakdown. The impact of process variation (e.g. line edge roughness, random dopant distribution, non-homogenity of the gate dielectric) on the device reliability will be investigated and potential solutions will be proposed. Aging models will be developed to predict device lifetime dependence on the statistical fluctuations of geometrical and technological parameters of nano-MOSFET. Model parameters will be calibrated with the hardware results of aging measurements. UNET will work on methodologies to design reliability experiments that allow characterizing the impact of PV on test structures, single cells or simple arrays, on 45nm & 32nm planar CMOS, and on Non-Volatile Memories. It will include the development of compact models including aging effects. AMS will execute lifetime measurements necessary for model development and the usage in SPICE simulators in 0.13um, 0.18um and 0.35um CMOS and HV technologies. The objective is to develop silicon based models for PV and reliability correlation. Lifetime measurements will be performed on appropriate test structures. Based on that data set, PV-aware parameter degradation models for NBTI and HCI effects will be developed at TUW. Since in particular degradation caused by NBTI is known to recover quickly once the stress is removed, emphasis will be put on a proper description of the dynamical properties of the degradation. 3 WP2 Review Meeting Milan, October 05, 2011

4. T2.4 Task (2/2) Task T2.4: Correlation between PV and reliability, reliability modeling (cont’) With future technology nodes it is becoming more and more critical to consider statistical and deterministic variations for ensuring the design goal at time of manufacturing as well as for the proposed lifetime. IMEP will investigate based on mixed mode TCAD simulation and on analytical models the SBD/BD failure occurrence impact at device level on device characteristics and at elementary circuit level on subsequent circuit functioning. These studies will be extended to new device architecture featuring thin silicon film (MugFET, GAA), which will be benchmarked in term of reliability robustness to bulk devices. This will require a detailed analysis of the SBD/BD occurrence and characterization on actual FD-SOI or GAA devices. The work will be carried out in collaboration with STF2. 4 WP2 Review Meeting Milan, October 05, 2011

5. Reliability: T2.4 Deliverables RefDeliverable/ ContributorsDue date D2.4.1Specification of considered degradation effects, modeling approaches and device parameters (UNGL, TUW) M6 DONE D2.4.2Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA) M24 DONE D2.4.3Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA) M33 Task Leader: Jong-mun.park@austriamicrosystems.com 5 WP2 Review Meeting Milan, October 05, 2011

6. D2.4.1 Considered degradation effects Contributions Effects -> Technologies HCINBTITDDBRTN/Trapping/ De-trapping SBD/BD HV mosAMS,TUW 65nm cmosUNCA 45nm cmosUNGL NVMUNET, NMX Thin SiIMEP 6 WP2 Review Meeting Milan, October 05, 2011

7. D2.4.1 Measurements Contributions Degradation mechanism FigureConditionsComments NBTIVTVG range T range LV HV MOS: Recoverable and permanent degradation components (AMS/TUW) HCIIdlin, Idsat, VT VG range T range HV MOS: degradation can not be predicted. Presence on Self-heating and NBTI stress during measurements (NBTI) PV effects on Reliability Idlin, Idsat, VT Mismatch VT, RTN HV MOS: NBTI/HCI tests on production lots, and corner lots, and correlation with tests before stress (AMS/TUW) 65nm: HCI tests and impact on mismatch (UNCA) NVM: impact of program/erase on Trapped Interface/Oxide charges (IUNET) 7 WP2 Review Meeting Milan, October 05, 2011

8. D2.4.1 Modeling approach PartnersTasks AMS-TUW. Develop a TCAD tool to analyze the HCI behaviour of HV-CMOS transistors IUNET-NMX. Refine their tool for 3D simulation of NVM cells under RTN and RDD.models for the trapping/detrapping process and its impact on V T fluctuation. Statistical models for SILC simulations UNCA.Statistical compact modelling of HCI fluctuation in 65nm technology IMEP.TCAD simulation and Compact modeling of SBD/BD effects in MMuG and GAA mosfets UNGL.Validate the GARAND simulations against 45 nm technology devices and statistical measurements available at ST-F..Introduce spatial distribution of the trapped charge in the oxide and channel region (HCI)..Introduce energy distribution of the traps in order to be able to simulate correlations and gate voltage dependence of the trapping.. Evaluate the possibility to simulate the statistical aspects of Time Dependent Dielectric Breakdown (TDDB).. Statistical compact modelling of NBTI, HCI, V T fluctuation (BSIM, PSP) AllImplementation in RelXpert environment to enable within Design flow:.Fresh simulation.Calculation of the aging using some analytical expression.Degradation of the SPICE parameters and updating the netlist.Re-simulation with degraded netlist 8 WP2 Review Meeting Milan, October 05, 2011

9. T2.4 Review Summary (1/2) Activity done so far, with highlights on technical results, and dissemination - D2.4.1 deliverable: done - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations (AMS & TUW), LV NMOS & PMOS (GOX:15 nm), 20V nLDMOS & pLDMOS (GOX: 7 nm) - Discuss with T2.5 the most interesting devices for the demonstrator, with T2.1 the process parameters to take into account. (All T2.4 members) - Initial physics-based analytical model for NBTI to implement in circuit simulator (UNGL) - Survey of degradation effects (TUW, UGLA) - Time dependent modeling of degradation for NBTI & HC (TUW, back-up slides) D2.4.2 deliverable (M24): Done - TCAD reliability simulations focused on LV devices in HV-CMOS process. - Hot-carrier degradation measurements for analytical & TCAD model developments. - Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node. 9 WP2 Review Meeting Milan, October 05, 2011

10. T2.4 Review Summary (2/2) Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI (UNGL). - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time. (UNGL) - Analytical NBTI and HC model developments for LV- & HV-CMOS - TCAD reliability simulations focused on HV-CMOS technology(AMS, TUW) - Digital IG noise simulation (UNET) - All T2.4 members Issues : Interaction need: - AMS & TUW: 0.35 µm LV-CMOS & HV-CMOS, D2.4.2 and D2.4.3 (output for T2.5) - UNET (partner: NMX): NVM, D2.4.2 and D2.4.3 - UNCA (partner: ST-I): 65 nm, D2.4.2 and D2.4.3 - UNGL (partner: STF2): 45 nm CMOS, D2.4.3 - IMEP (partner: STF2): Finfets, MUG, GAA, D2.4.3 10 WP2 Review Meeting Milan, October 05, 2011

11. T2.4 Back-up slides 11 1.NBTI & Hot-Carrier Activities (TUW) 2.Subthreshold Slope Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node (UNCA & NXP) 3.Digital I G Noise Simulations (UNET) 4.A Methodology for Simulating the Statistical Aspect of P/NBTI and Hot-Carrier Degradation (UNGL) 5.Hot-Carrier Lifetime Models for High-Voltage Transistors (AMS) WP2 Review Meeting Milan, October 05, 2011

12. 12 1. NBTI & Hot-Carrier Activities (  D2.4.3) Vienna Universty of Technology (TUW) WP2 Review Meeting Milan, October 05, 2011

13. 13 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: NBTI Discrete capture/emission time map (CET) of τ c and τ e –Strong bias dependence of τ c –Strong temperature dependence of both τ c and τ e –Note: τ c = τ c (V H ) and τ c = τ c (V L )

14. 14 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: NBTI What is the use of CET time map? –Reconstruct the temporal behavior (jus like Fourier transform) –Macroscopic version (expectation value) Example CET map for an SiON pMOS with EOT = 2.2 nm

15. 15 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: NBTI Analytical model for the CET map –Two bivariate normal distributions for the activation energies –Parameters bias-dependent

16. 16 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: NBTI Analytical model for the CET map –Allow analytical integration for DC and AC stress

17. 17 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: NBTI Examples for analytical NBTI model –Verified for SiO 2, SiON, HfSiO, and HfSiON

18. 18 WP2 Review Meeting Milan, October 05, 2011 Future Activities: NBTI Distribution of activation energies –Microscopic origin of the effective activation energy distribution –Must be linked to microscopic defect model

19. 19 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD The model Features of previous approaches Linking all the levels related to this effect A physics-based model contains Carrier transport module Module describing the defect build-up Module for simulation degraded devices Carrier transport Full-band Monte-Carlo device simulator MONJU Allows to thoroughly evaluate the DF For a particular device architecture

20. 20 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD The linear drain current degradation –I dlin0 – current in a “fresh” device, ΔI dlin – its change –V t – threshold voltage, ΔV t – its shift –μ 0 – mobility of a “fresh” device, Δμ – mobility change Mobility degraded due to N it –α sc – prefactor –ΔV t ≈ 0 in our devices A. Bravaix et al., IRPS-2009 N. Stojadinovic et al., Electron Lett., 1995

21. 21 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD Analytical approach to HCD modeling –Based on the TCAD version –Incorporates interplay between single- and multiple-carrier processes for Si-H bond-breakage –Controlled by the carrier acceleration integral (AI) –Average N it,SE is introduced –Analytical expression for I(x)Integratable Average N it → analytical

22. 22 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD Slopes of the AI peak –described by Fermi-Dirac derivatives –on a log-scale –piecewise functions Parameters varying with V ds : –slope of I 2 : β –extension of the ledge I 4 : x 4 -x 3 –heights: A 2, A 3, A 4

23. 23 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD Parameters vs. V ds –linear dependence on V ds –scattering in parameters: –stochastic noise –from TCAD model –based on Monte-Carlo Dependences: –useful to interpolate values –and calculate AI –instead of time-consuming –Monte-Carlo method Analyze impact of statistical variations on HCD

24. 24 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD Average N it concentration: –contains components J i related to I i –expressed via exponential integrals –explicit expressions for J i :

25. 25 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD Representation of the SE-component –TCAD results ↔ experiment –Damage produced by the SE-mechanism –Good agreement between TCAD and analytical models

26. 26 WP2 Review Meeting Milan, October 05, 2011 Present/Done Activities: HCD SE- and ME-contributions are now considered –Rather good agreement between: –experiment –TCAD model results –analytical model results

27. 27 WP2 Review Meeting Milan, October 05, 2011 Future Activities: HCD Model Oxide thickness varies: –T ox = 0.4, 0.6, 0.8, 1.0, 1.2, 1.4, 1.6, 1.9 T n –T n – nominal thickness

28. 2. Subthreshold Slope Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node (Ref.: D2.4.2) Universty of Calabria (UNCA) in collaboration with NXP 28 WP2 Review Meeting Milan, October 05, 2011

29. 29 PURPOSE To characterize and to model the HC-induced subthreshold slope variability in 65 nm and 45 nm technology node WP2 Review Meeting Milan, October 05, 2011

30. 30 WP2 Review Meeting Milan, October 05, 2011 Devices Under Test The reported statistical analysis is based on a large overall sample population of one thousand transistors

31. 31 WP2 Review Meeting Milan, October 05, 2011 Modeling of HC-indiced Subthreshold Slope Variability HC stress causes an increase in the interface state density D it and thus in the interface capacity C it which induces a change in S Defect depassivation is assumed to be a Poisson process K HC parameter takes into account for the non-uniform defect depassivation along the channel direction

32. 32 WP2 Review Meeting Milan, October 05, 2011 Model Suitability Experimental data are well fitted by the proposed model, where median  S is used as an input and K HC is extrapolated by interpolation of experimental data The slope of this plot is very close to 0.5, hence confirming the hypothesis of Poisson process

33. 33 WP2 Review Meeting Milan, October 05, 2011 Impact of the HC-Induced Variability on the Overall Variability A significant increase of the overall  S mismatch is observed for both technologies

34. 34 WP2 Review Meeting Milan, October 05, 2011 Correlation coefficient is around 0.5 for both technologies Correlation between V T and S

35. Digital I G noise simulations 3. Digital I G noise simulations (  (  D2.4.3) Consorzio Nazionale Interuniversitario per la Nanoelettronica (UNET) 35 WP2 Review Meeting Milan, October 05, 2011

36. 36 WP2 Review Meeting Milan, October 05, 2011 Physical model reproducing digital I G fluctuations observed in ultra-thin dielectrics after SBD Current fluctuations are modeled assuming that some traps in the percolation path switch between two unstable configurations, corresponding to neutral and negatively charged O vacancies. Digital I G Noise Simulations Ref: L. Morassi et al, “ A Physical Model for post- breakdown digital gate current noise,” submitted to IEEE Electron Device Letters, 2011

37. 4. A Methodology for Simulating the Statistical Aspect of P/NBTI and Hot-Carrier Degradation (  D2.4.3) The University of Glasgow (UNGL) 37 WP2 Review Meeting Milan, October 05, 2011

38. 38 WP2 Review Meeting Milan, October 05, 2011 Purpose We developed a methodology for simulating the statistical aspect of P/NBTI and hot carrier degradation in 32nm RVT N/PMOS. Random trapped charges due to P/NBTI stress are assigned to interface degradation. The threshold-voltage shift is observed and its variations are analyzed.

39. 39 WP2 Review Meeting Milan, October 05, 2011 3-D Simulation Method The N/PMOS are first calibrated both in doping profiles and electrical characteristics. After stress, the traps are randomly assigned at interface according to local nominal trap sheet density.

40. 40 WP2 Review Meeting Milan, October 05, 2011 Device Degradation under Stress Under PBTI/PBTI stress, the interface trapped charge accumulates, leading to threshold-voltage shift and device performance degradation.

41. 41 WP2 Review Meeting Milan, October 05, 2011 PBTI/NBTI Variability NMOS PMOS Both number and placement of traps varies, which leads to variation of PBTI/NBTI effects.

42. 42 WP2 Review Meeting Milan, October 05, 2011 Trap Density Dependence The threshold-voltage shift is proportional to trap density and its standard deviation is proportional to the sqrt of trap density. Both are proportional to EOT. PMOS EOT is slightly larger than NMOS.

43. 5. Hot-Carrier Degradation Measurements (Ref.: D2.4.2) 0.35 µm HV-CMOS Technology - LV-NMOSI, LV-NMOSIM - NMOSI20T - PMOS20T austriamicrosystems AG 43 WP2 Review Meeting Milan, October 05, 2011

44. Proposal for a Lifetime Model for High-Voltage Devices Modified Hu- model, empirical 1. Kirk effect: change of location of maximum impact ionisation: depending on gate-voltage. 2. Occurance of multiple locations of significant impact ionisation: depending on bias. 3. Electron injection, hole injection, interface trap generation simultaneously. 4. Self heating.  No generally accepted HC model is available.  Formulation of a HC model where V g and T is an additional parameter: 44 WP2 Review Meeting Milan, October 05, 2011

45. NMOSIM: Cross Section 45 WP2 Review Meeting Milan, October 05, 2011

46. LV-NMOSIM: Transfer Curves 46 WP2 Review Meeting Milan, October 05, 2011 V DS =0.1 V for Lg=0.5 µm V Gstress =2 V and V Dstress =7 V Stress time: 1x10 5 sec V DS =5.0 V for Lg=0.5 µm V Gstress =2 V and V Dstress =7 V Stress time: 1x10 5 sec

47. 47 WP2 Review Meeting Milan, October 05, 2011 Output curves V Gstress =2 V and V Dstress =7 V Stress time: 1x10 5 sec Degradation versus stress time V Gstress =2 V and V Dstress =7 V LV-NMOSIM: Output Curves, Degadation versus Stress Time

48. 48 WP2 Review Meeting Milan, October 05, 2011 Lifetime versus substrate current Id x lifetime versus ionization-rate Ionization-rate and Lg effects on the lifetime LV-NMOSIM: Lifetime-Substrate Current, Ionization-Rate and Lg Effects on the Lifetime

49. 49 WP2 Review Meeting Milan, October 05, 2011 LV-NMOSIM: Charge Pump Measurements Time evolution of the Icp versus Vgh Interface state density at the channel region

50. 50 WP2 Review Meeting Milan, October 05, 2011 HV-NMOS (NMOSI20T) and HV-PMOS (PMOS20T) NMOSI20T PMOS20T

51. 51 WP2 Review Meeting Milan, October 05, 2011 NMOSI20T: Id x Lifetime versus Ionization-Rate

52. 52 WP2 Review Meeting Milan, October 05, 2011 Vg=-1.6V Vg=-1.9VVg=-3.6V PMOS20T: Small Hot-Carrier Degradation

53. Corner Split on Isolated NMOS Transistor (NMOSI) 53 WP2 Review Meeting Milan, October 05, 2011 NMOSI corner specification Standard (2) Worst case power (5) Worst case speed (8) Worst case one (11) Worst case zero (14) Leff N/P typ. Vt NMOS typ. Vt PMOS typ. Leff N/P < Vt NMOS < Vt PMOS < Leff N/P > Vt NMOS > Vt PMOS > Leff N/P typ. Vt NMOS Leff N/P typ. Vt NMOS > Vt PMOS < Stage Description Recipes123456789101112131415 Vt implantBF2, 70K, 7.7E12xxx BF2, 70K, 7.4E12 xxxxxx BF2, 70K, 8.0E12 xxx xxx poly 1 maskDI-CD = 0.40µmxxx xxxxxx DI-CD = 0.37µm xxx DI-CD = 0.44µm xxx

54. Effective Channel-Length versus Corner Lots 54 WP2 Review Meeting Milan, October 05, 2011

55. Idlin-Shift after 150 sec Stress of Corner Lots 55 WP2 Review Meeting Milan, October 05, 2011

56. 56 WP2 Review Meeting Milan, October 05, 2011 Idsat-Shift after 150 sec Stress of Corner Lots

57. 57 WP2 Review Meeting Milan, October 05, 2011 Conclusions D2.4.1: done - Specification of considered degradation effects, modelling approaches and device parameters - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations - Initial physics-based analytical model for NBTI to implement in circuit simulator - Time dependent modeling of degradation for NBTI & HC D2.4.2 (M24): done - TCAD reliability simulations focused on LV devices in HV-CMOS process - Hot-carrier degradation measurements for analytical & TCAD model developments - Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node D2.4.3 (M33): on going - Statistical compact Models will be extracted at different levels of NBTI and PBTI. - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time - Analytical NBTI and HC model developments for LV- & HV-CMOS - TCAD reliability simulations focused on HV-CMOS technology - Digital IG noise simulation