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**Collaborators EXPERIMENT Duc Nguyen, 3rd year student UNM/AFRL RVSE**

Camron Kouhestani, 3rd year student UNM/AFRL RVSE Rod Devine, Think Strategically/AFRL RVSE THEORY Ken Kambour, SAIC/AFRL RVSE Harry Hjalmarson, Sandia National Labs. TECHNOLOGIES 130 nm IBM Bulk – nitrided SiO2 90 nm IBM Bulk – nitrided SiO2 45 nm IBM SOI – nitrided SiO2 32 nm TI – HfSiON Bulk

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**NBTI Experiment Type I Gate dielectrics – SiO2, lightly nitrided SiO2**

Room temperature NBTI due to interface state generation DVth = A t a 0.16 ≤ a ≤ 0.25 Type II Gate dielectrics- nitrided SiO2, HfSiON Room temperature NBTI due to interface state generation and hole tunneling from the inversion layer into neutral traps in the near interface region. Oxide traps charge quickly but also relax quickly if bias is removed/reduced. Need to measure NBTI dynamically to capture full effect of charging

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**Comparative Stress and Recovery**

Data for 130 nm at Room Temp. Example of room temperature NBTI in 130 nm channel length devices with 3.2 nm nitrided SiO2 gate dielectric. Stressing (Vgs = -3.3 V) Recovery (Vgs = 0 V) 4

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**Evolution of NBTI Study (Experiment)**

Stress Short time regime (tstress < 1 sec) Model DVth(t) assuming full field dependent tunneling only oxide trapped charge relevant Long time regime (tstress > 100 sec) Model DVth(t) assuming oxide trapped charge saturated only interface state term evolves. Recovery Model short time regime as de-trapping via tunneling Model of long time interfacial trap relaxation (exists) Develop an NBTI model enabling prediction of frequency and duty cycle dependence

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**Circuit Response - Cao's approach**

Uses the Alam model for NBTI to determine the ΔVth as a function of duty cycle and age .(only interface states) Determines the effect of changing the PMOS threshold voltage, the capacitive load, and the input slew rate on the delay time of a CMOS NAND gate composed of PMOS and NMOS devices. Once this is done, treats the NAND gates as single devices rather than combinations of MOSFETs. Apply to multiple standard digital logic (benchmark)circuits used to test the timing. (ISCAS ’89)

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RVSE Approach Develop our own formula, either theoretical or empirical, for ΔVth as a function of duty cycle and age. Recreate Cao's basic results. Currently using Predictive Technology Model (PTM) SPICE device models for 65 nm MOSFETS. PTM (ptm.asu.edu) is a standard set of device libraries. Channel lengths from 180 nm down to 22 nm. Ultimately implement modeling software capable of treating much larger scale circuits

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**Xyce Xyce was developed at Sandia National Labs. Why choose Xyce?**

Designed for large scale problems. (23,000,000 devices have been simulated) Potential access to source code. Can model both digital devices (NAND, NOR, AND, & OR gates) and transistors. Access to local expertise. Xyce has radiation modeling developed which we could obtain in the future if we wish.

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CMOS NOR and NAND Gates

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Effect of Vth on td As the threshold voltage changes, for example due to NBTI, the delay time rises for both NOR (green) and NAND (yellow) gates.

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**Effect of ti on Delay and to**

As the input slew rate rises, for example if one input for the NAND gate is the output of a prior NAND gate experiencing a Vth shift, the delay (blue points) and output slew rate (red points) rises.

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**C17 Benchmark Circuit C432 Benchmark Circuit Working in Xyce**

Simulation of transient switching of one input takes 3 seconds. C432 Benchmark Circuit 233 logic gates including other gates made by sets of NANDS 752 PMOS and 752 NMOS devices

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Ring Oscillator Implemented a ring oscillator to determine the effect of ΔVth on frequency 11 NAND gates using the 65 nm PTM models If ΔVth=0.1 volts, the frequency changed by 15%

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**Conclusions Experiment The dynamic measurement system works well**

We are close to being able to model the complete short time long time behavior of NBTI Need access to a much larger reservoir of devices ideally with controlled process variations Theory Modeling of the effects of NBTI on limited circuit size examples is operative Implementing the modeling in Xyce to predict response of much more complex circuits

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