2Collaborators EXPERIMENT Duc Nguyen, 3rd year student UNM/AFRL RVSE Camron Kouhestani, 3rd year student UNM/AFRL RVSERod Devine, Think Strategically/AFRL RVSETHEORYKen Kambour, SAIC/AFRL RVSEHarry Hjalmarson, Sandia National Labs.TECHNOLOGIES130 nm IBM Bulk – nitrided SiO290 nm IBM Bulk – nitrided SiO245 nm IBM SOI – nitrided SiO232 nm TI – HfSiON Bulk
3NBTI Experiment Type I Gate dielectrics – SiO2, lightly nitrided SiO2 Room temperature NBTI due to interface state generation DVth = A t a0.16 ≤ a ≤ 0.25Type II Gate dielectrics- nitrided SiO2, HfSiONRoom temperature NBTI due to interface state generation and holetunneling from the inversion layer into neutral traps in the near interfaceregion. Oxide traps charge quickly but also relax quickly if bias isremoved/reduced.Need to measure NBTI dynamically to capture full effect of charging
4Comparative Stress and Recovery Data for 130 nm at Room Temp.Example of room temperature NBTI in 130 nm channel length devices with3.2 nm nitrided SiO2 gate dielectric.Stressing (Vgs = -3.3 V)Recovery (Vgs = 0 V)4
5Evolution of NBTI Study (Experiment) StressShort time regime (tstress < 1 sec)Model DVth(t) assuming full field dependent tunnelingonly oxide trapped charge relevantLong time regime (tstress > 100 sec)Model DVth(t) assuming oxide trapped charge saturatedonly interface state term evolves.RecoveryModel short time regime as de-trapping via tunnelingModel of long time interfacial trap relaxation (exists)Develop an NBTI model enabling prediction of frequency and dutycycle dependence
6Circuit Response - Cao's approach Uses the Alam model for NBTI to determine the ΔVth as a function of duty cycle and age .(only interface states)Determines the effect of changing the PMOS threshold voltage, the capacitive load, and the input slew rate on the delay time of a CMOS NAND gate composed of PMOS and NMOS devices.Once this is done, treats the NAND gates as single devices rather than combinations of MOSFETs.Apply to multiple standard digital logic (benchmark)circuits used to test the timing. (ISCAS ’89)
7RVSE ApproachDevelop our own formula, either theoretical or empirical, for ΔVth as a function of duty cycle and age.Recreate Cao's basic results.Currently using Predictive Technology Model (PTM) SPICE device models for 65 nm MOSFETS.PTM (ptm.asu.edu) is a standard set of device libraries.Channel lengths from 180 nm down to 22 nm.Ultimately implement modeling software capable of treating much larger scale circuits
8Xyce Xyce was developed at Sandia National Labs. Why choose Xyce? Designed for large scale problems. (23,000,000 devices have been simulated)Potential access to source code.Can model both digital devices (NAND, NOR, AND, & OR gates) and transistors.Access to local expertise.Xyce has radiation modeling developed which we could obtain in the future if we wish.
10Effect of Vth on tdAs the threshold voltage changes, for example due to NBTI, the delay time rises for both NOR (green) and NAND (yellow) gates.
11Effect of ti on Delay and to As the input slew rate rises, for example if one input for the NAND gate is the output of a prior NAND gate experiencing a Vth shift, the delay (blue points) and output slew rate (red points) rises.
12C17 Benchmark Circuit C432 Benchmark Circuit Working in Xyce Simulation of transient switching of one input takes 3 seconds.C432 Benchmark Circuit233 logic gates including other gates made by sets of NANDS752 PMOS and 752 NMOS devices
13Ring OscillatorImplemented a ring oscillator to determine the effect of ΔVth on frequency11 NAND gates using the 65 nm PTM modelsIf ΔVth=0.1 volts, the frequency changed by 15%
14Conclusions Experiment The dynamic measurement system works well We are close to being able to model the completeshort time long time behavior of NBTINeed access to a much larger reservoir of devicesideally with controlled process variationsTheoryModeling of the effects of NBTI on limited circuit sizeexamples is operativeImplementing the modeling in Xyce to predict responseof much more complex circuits