1. 9/20/6Lecture 3 - Instruction Set - Al1 Address Decoding for Memory and I/O

2. 9/20/6Lecture 3 - Instruction Set - Al2 Address Decoding  Address Decoding Designs Full Address Decoding Partial Address Decoding Block Address Decoding  Implementation Random, Decoders, PROM, FPGA

3. 9/20/6Lecture 3 - Instruction Set - Al3 Address Decoding  Required for a microcomputer where memory and I/O support are essential  Needed for embedded system when on chip microcontroller memory is not sufficient

4. 9/20/6Lecture 3 - Instruction Set - Al4 The Memory Space  2 basic approaches Memory mapped system – main memory and I/O space are just different addresses or regions – or memory mapped I/O (MMIO)  Addressing is the same pins for memory and I/O  Advantage – less pin and hardware complexity Port Mapped I/O – have unique pins (signals) that differentiate memory and I/O address spaces  Advantage – If limited memory, memory is memory  Advantage – Large I/O space

5. 9/20/6Lecture 3 - Instruction Set - Al5 Other architectures  Harvard Architecture Separate memory spaces for instructions and data Requires pin(s) to differentiate I/O is MMIO  Check these out on www.wikipedia.com

6. 9/20/6Lecture 3 - Instruction Set - Al6 The 68000 Memory Space  23 address lines 2 23 words with UDS* and LDS*  This is 8M words or 16M bytes

7. 9/20/6Lecture 3 - Instruction Set - Al7 Address Map  When implementing a system the designer creates a memory map.  Map would include where RAM, ROM and I/O are.

8. 9/20/6Lecture 3 - Instruction Set - Al8 Full address decoding  Each addressable location within the memory components responds to only a single unique address.

9. 9/20/6Lecture 3 - Instruction Set - Al9 Example of full address decoding

10. 9/20/6Lecture 3 - Instruction Set - Al10 Ex continued

11. 9/20/6Lecture 3 - Instruction Set - Al11 Partial Address Decoding  Some of address lines are unused  Least complex and most inexpensive  Each component will actually respond to several addresses

12. 9/20/6Lecture 3 - Instruction Set - Al12 Partial Address decoding example

13. 9/20/6Lecture 3 - Instruction Set - Al13 Block Address decoding  Compromise between full and partial.  Don’t decode all of address lines but do decode more than the bare minimum.  Less repeated addresses for each populated device

14. 9/20/6Lecture 3 - Instruction Set - Al14 Designing the decode logic  Multiple methods of implementing the decode logic  One method is of course to implement it with “random logic” – i.e., AND gates, OR gates, inverters, NAND gates, NOR gates  Advantage – speed  Disadvantage – possibly the number of chips

15. 9/20/6Lecture 3 - Instruction Set - Al15 Decoders  USE m-line-to-n-line decoders  Decode an m-bit input into one of n outputs where n = 2 m  Popular 74LS138 – 3-to-8 decoder  Another 74LS154 – 4-to-16 decoder

16. 9/20/6Lecture 3 - Instruction Set - Al16 Decoder Truth table

17. 9/20/6Lecture 3 - Instruction Set - Al17 Example of decoder use

18. 9/20/6Lecture 3 - Instruction Set - Al18 Implementation

19. 9/20/6Lecture 3 - Instruction Set - Al19 PROMS  A PROM can also be use to implement logic functions  Can use it to do address decoding

20. 9/20/6Lecture 3 - Instruction Set - Al20 Example of PROM use  Decoder design must be cheap and versitle.

21. 9/20/6Lecture 3 - Instruction Set - Al21 PROM Programming

22. 9/20/6Lecture 3 - Instruction Set - Al22 PROM System  Advantage- Ability to select blocks of differing size Versitility

23. 9/20/6Lecture 3 - Instruction Set - Al23 FPGA, PLA, PAL  Programmable Logic Arrays AND plane – OR plane  Programmable Array Logic Limited PLA  FPGA – A network of CLBs

24. 9/20/6Lecture 3 - Instruction Set - Al24 PAL vs PLA  In a PAL the ouput’s connection to product terms is fixed  More limited logic equation support

25. 9/20/6Lecture 3 - Instruction Set - Al25 Special devices  There are also special chips specifically designed for address decoding  Some may be designed for a specific family of chips