2. 5/24/2016 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Defects, Failures and Faults

3. Outline Physical defects Failure modes Faults Stuck-at faults Fault lists Bridging faults Shorts and opens faults Temporary faults Noise faults

4. Hard Vs Soft Failures Hard failure: Permanent Soft failure: Temporary Transient >> External Factors Intermittent >> Wearout Failure Classification

6. Failure Rate Vs Product Lifetime

9. Physical Defects  Metalization and metal semiconductor – Open metal at oxide steps – Wire bonding failure – Inter-metallic compound formation – Electromigration

10. Electromigration Metallization Failure mechanism Mass transport of metal atoms Serious migration Aluminum and copper for J>10 5 Amp/cm 2 Gold has higher limits Mean time to failure of a wire Here A is a constant based on the cross-sectional area of the interconnect, J is the current density, Ea is the activation energy (e.g. 0.7 eV for grain boundary diffusion in aluminum), k is the Boltzmann constant, T is the temperature and n a scaling factor

11. Electromigration (a) Open in a line (b) Short between two lines (whisker) (c) Short between lines on different layers (hillock)

13. Physical Defects Surface and bulk effect – Passivation pits and cracks – Gate oxide breakdown –Pinholes or thin spots in oxide –Electrical over-stress – Surface potential instability

19. Mapping Physical Defect into Faults 1 Both the defective resistance in bipolar and a the oxide breakdown between the source and drain of NMOS transistor form a short failure mode Both cases are mapped into A stuck-at 0 fault

20. Mapping Physical Defect into Faults 2 Physical defect: A missing poly NMOS is missing the gate Failure mode: an open Fault: stuck open

21. Mapping Physical Defect into Faults 3

22. Types of Faults

23. More Fault Types

24. SA Faults: Example

25. Multiple Stuck-at Faults Combinations of m SA faults on N lines Total:

26. Fault Properties Given two faults F1 and F2 with two tests T1 and T2 Equivalence: F1 is equivalent to F2 if T1 = T2 Any test detecting F1, detects F2 and vice versa Dominance: F1 dominates F2 if T2  T1 a test detecting F2 detects also F1 the relation is not symmetric

27. Fault Collapsing 1{A/0, B/0, H/0} 2{C/1, D/1, F/1, G/0} 3{E/0, G/0, V/0}merge 4{H/1, V/1, Z/1} 5{F/0, G/1} 6A/1  H/1, thus A/1 can represent H/1 and all its equivalent faults in class 4 7C/0  F /0, thus C/0 can represent F/0 and all its equivalent faults in class 5 8V/0  Z /0, but V/0 belongs to equivalence class 3, merged into class 2. Any fault from this class is dominated by Z/0. 9B/1  H /1 10D/0  F/0 11E/1  V /1 Collapsed set of faults {A/0, A/1, B/1, C/0, C/1, D/0, E/1} Consider all 20 single stuck-at faults in this circuit and use fault equivalence and fault dominance to reduce the list of fault to test

28. Circuit Redundancy Redundant circuits are not fully testable

29. Bridging Faults r lines are unintentionally shorted r = 2 is more realistic to test

30. Functional Change Z_bar=AB + CD Z A B D C Z_bar = (A+C)(B+D) A B D C Z

31. Transistor Faults MOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the measurement of quiescent current (I DDQ ).

32. Stuck-Open Example Two-vector s-open test can be constructed by ordering two s-at tests A B V DD C pMOS FETs nMOS FETs Stuck- open 1010 0000 01(Z) Good circuit states Faulty circuit states Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1)

33. Stuck-Short Example A B V DD C pMOS FETs nMOS FETs Stuck- short 1010 0 (X) Good circuit state Faulty circuit state Test vector for A s-a-0 I DDQ path in faulty circuit

34. NMOS Transistors

35. CMOS Open A Z 1 2 3 4 5 6 7 1 0 0 0 0 Q 0 1 Q Q Q Q Complete the stuck open fault table 4 6 X X X X X X 1 3 2 5 X A Vin Z Vout 7

36. CMOS Open 7 4 6 X X X X X X 1 3 2 5 X A Vin Z Vout A Z 1 2 3 4 5 6 7 1 0 Q Q Q 0 0 0 Q 0 1 1 1 1 Q Q Q Q

37. CMOS Shorts A Z 1 2 3 4 5 6 0 1 0 0 1 0 0 X 4 6 1 3 2 5 A Vin Z Vout Complete the stuck open fault table

38. CMOS Shorts A Z 1 2 3 4 5 6 0 1 0 1 1 0 0 0 1 0 0 1 1 0 X X 4 6 1 3 2 5 A Vin Z Vout

39. Yield

40. Errors Loading of wafers into oxidation furnace http://www.leb.eei.uni-erlangen.de/lehre/mm/images/oxidation/furnace3.jpg

41. Instabilities

43. Substrate

46. Disturbances

47. Lateral Effects