1. Test de Circuitos Integrados

2. Índice I: Introducción al Test de Circuitos Integrados
II: Métodos de Test
III: Design for testability

3. VLSI Realization Process
Customer’s need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabrication
Manufacturing test
Chips to customer

4. Definitions
Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.
Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.
Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

5. Verification vs. Test Verifies correctness of design.
Performed by simulation, hardware emulation, or formal methods.
Performed once prior to manufacturing.
Responsible for quality of design.
Verifies correctness of manufactured hardware.
Two-part process:
1. Test generation: software process executed once during design
2. Test application: electrical tests applied to hardware
Test application performed on every manufactured device.
Responsible for quality of devices.

6. Roles of Testing
Detection: Determination whether or not the device under test (DUT) has some fault.
Diagnosis: Identification of a specific fault that is present on DUT.
Device characterization: Determination and correction of errors in design and/or test procedure.
Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

7. Problems of Ideal Tests
Ideal tests detect all defects produced in the manufacturing process.
Ideal tests pass all functionally good devices.
Very large numbers and varieties of possible defects need to be tested.
Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.

8. Real Tests
Based on analyzable fault models, which may not map on real defects.
Incomplete coverage of modeled faults due to high complexity.
Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.
Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

9. Types of Testing
Verification testing, characterization testing, or design debug
Verifies correctness of design and of test procedure – usually requires correction to design
Manufacturing testing
Factory testing of all manufactured chips for parametric faults and for random defects
Acceptance testing (incoming inspection)
User (customer) tests purchased parts to ensure quality

10. Testing Principle

11. Manufacturing Test Determines whether manufactured chip meets specs
Must cover high % of modeled faults
Must minimize test time (to control cost)
No fault diagnosis
Tests every device on chip
Test at speed of application or speed guaranteed by supplier

12. Types of Manufacturing Tests
Wafer sort or probe test – done before wafer is scribed and cut into chips
Includes test site characterization – specific test devices are checked with specific patterns to measure:
Gate threshold
Polysilicon field threshold
Poly sheet resistance, etc.
Packaged device tests

13. Sub-types of Tests
Parametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap
Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive

14. Two Different Meanings of Functional Test
ATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing test
Automatic Test-Pattern Generation World – testing with verification vectors, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %)

15. Test Programming

16. Automatic Test Equipment (ATE)

17. T6682 ATE Specifications Uses 0.35 mm VLSI chips in implementation
1024 pin channels
Speed: 250, 500, or 1000 MHz
Timing accuracy: +/- 200 ps
Drive voltage: -2.5 to 6 V
Clock/strobe accuracy: +/- 870 ps
Clock settling resolution: ps
Pattern multiplexing: write 2 patterns in one ATE cycle
Pin multiplexing: use 2 pins to control 1 DUT pin

18. Pattern Generation
Sequential pattern generator (SQPG): stores 16 Mvectors of patterns to apply to DUT, vector width determined by # DUT pins
Algorithmic pattern generator (ALPG): 32 independent address bits, 36 data bits
For memory test – has address descrambler
Has address failure memory
Scan pattern generator (SCPG) supports JTAG boundary scan, greatly reduces test vector memory for full-scan testing
2 Gvector or 8 Gvector sizes

19. Fault Modeling Why model faults? Some real defects in VLSI and PCB
Common fault models
Stuck-at faults
Single stuck-at faults
Fault equivalence
Fault dominance and checkpoint theorem
Classes of stuck-at faults and multiple faults
Transistor faults

20. Some Real Defects in Chips
Processing defects
Missing contact windows
Parasitic transistors
Oxide breakdown
. . .
Material defects
Bulk defects (cracks, crystal imperfections)
Surface impurities (ion migration)
Time-dependent failures
Dielectric breakdown
Electromigration
Packaging failures
Contact degradation
Seal leaks

21. Common Fault Models Single stuck-at faults
Transistor open and short faults
Memory faults
PLA faults (stuck-at, cross-point, bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults

22. Single Stuck-at Fault Three properties define a single stuck-at fault
Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults
Faulty circuit value
Good circuit value c j
0(1)
s-a-0 a d
1(0) g 1 h z i 1 b e 1 k f
Test vector for h s-a-0 fault

23. Fault Equivalence
Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches).
Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2.
If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.
Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

24. Equivalence Rules
sa0 sa1
sa0
sa1
AND
NAND OR
NOR
WIRE
NOT
FANOUT

25. Equivalence Example sa0 sa1 Faults in red removed by equivalence
collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 20
Collapse ratio = = 0.625 32

26. Fault Dominance
If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1.
Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list.
When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example.
In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set.
If two faults dominate each other then they are equivalent.

27. Dominance Example All tests of F2 F1 s-a-1 001 F2 110 010 000 s-a-1
000
101
100
s-a-1 F2
011
Only test of F1
s-a-1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set

28. Checkpoints
Primary inputs and fanout branches of a combinational circuit are called checkpoints.
Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.
Total fault sites = 16
Checkpoints ( ) = 10

29. Classes of Stuck-at Faults
Following classes of single stuck-at faults are identified by fault simulators:
Potentially-detectable fault -- Test produces an unknown (X) state at primary output (PO); detection is probabilistic, usually with 50% probability.
Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault.
Hyperactive fault -- Fault induces much internal signal activity without reaching PO.
Redundant fault -- No test exists for the fault.
Untestable fault -- Test generator is unable to find a test.

30. Multiple Stuck-at Faults
A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values.
The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1.
A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare.
Statistically, single fault tests cover a very large number of multiple faults.

31. Transistor (Switch) Faults
MOS transistor is considered an ideal switch and two types of faults are modeled:
Stuck-open -- a single transistor is permanently stuck in the open state.
Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.
Detection of a stuck-open fault requires two vectors.
Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).

32. Stuck-Open Example VDD A B C Vector 1: test for A s-a-0
(Initialization vector)
Vector 2 (test for A s-a-1)
pMOS
FETs
VDD
Two-vector s-op test
can be constructed by
ordering two s-at tests A 1
Stuck-
open B C
1(Z)
Good circuit states
nMOS
FETs
Faulty circuit states

33. Stuck-Short Example VDD A B C Test vector for A s-a-0 pMOS FETs
IDDQ path in
faulty circuit A 1
Stuck-
short B
Good circuit state C
0 (X)
nMOS
FETs
Faulty circuit state

34. Problem with stuck-at model: CMOS short fault
Causes short circuit between
Vdd and GND for A=C=0, B=1
Possible approach:
Supply Current Measurement (IDDQ)
but: not applicable for gigascale integration
[Adapted from Copyright 1996 UCB]

35. Fault Simulation Problem and motivation Fault simulation algorithms
Serial
Parallel
Deductive
Concurrent
Random Fault Sampling

36. Problem and Motivation
Fault simulation Problem: Given
A circuit
A sequence of test vectors
A fault model
Determine
Fault coverage - fraction (or percentage) of modeled faults detected by test vectors
Set of undetected faults
Motivation
Determine test quality and in turn product quality
Find undetected fault targets to improve tests

37. Fault simulator in a VLSI Design Process
Verification
input stimuli
Verified design
netlist
Fault simulator
Test vectors
Modeled
fault list
Remove
tested faults
Test
compactor
Delete
vectors
Fault
coverage ?
Low
Test
generator
Add vectors
Adequate
Stop

38. Fault Simulation Scenario
Circuit model: mixed-level
Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals
High-level models (memory, etc.) with pin faults
Signal states: logic
Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits
Four states (0, 1, X, Z) for sequential MOS circuits
Timing:
Zero-delay for combinational and synchronous circuits
Mostly unit-delay for circuits with feedback

39. Fault Simulation Scenario (continued)
Mostly single stuck-at faults
Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use
Equivalence fault collapsing of single stuck-at faults
Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis
Fault sampling -- a random sample of faults is simulated when the circuit is large

40. Fault Simulation Algorithms
Serial
Parallel
Deductive
Concurrent
Differential

41. Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault
Simulate modified netlist, vector by vector, comparing responses with saved responses
If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory
Most faults, including analog faults, can be simulated

42. Serial Algorithm (Cont.)
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits
Alternative: Simulate many faults together
Test vectors
Fault-free circuit
Comparator
f1 detected?
Circuit with fault f1
Comparator
f2 detected?
Circuit with fault f2
Comparator
fn detected?
Circuit with fault fn

43. Parallel Fault Simulation
Compiled-code method; best with two-states (0,1)
Exploits inherent bit-parallelism of logic operations on computer words
Storage: one word per line for two-state simulation
Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length
Speed up over serial method ~ w-1
Not suitable for circuits with timing-critical and non-Boolean logic

44. Parallel Fault Sim. Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
c s-a-0 detected a b e c
s-a-0 g d f
s-a-1

45. Deductive Fault Simulation
One-pass simulation
Each line k contains a list Lk of faults detectable on k
Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists
PO fault lists provide detection data
Limitations:
Set-theoretic rules difficult to derive for non-Boolean gates
Gate delays are difficult to use

46. Deductive Fault Sim. Example
Notation: Lk is fault list for line k
kn is s-a-n fault on line k
Le = La U Lc U {e0}
= {a0 , b0 , c0 , e0} 1
{a0} a
{b0 , c0} 1 e b 1
{b0} c 1 g f d
Lg = (Le Lf ) U {g0}
= {a0 , c0 , e0 , g0} U
{b0 , d0}
{b0 , d0 , f1}
Faults detected by
the input vector

47. Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit.
A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any.
All events of fault-free and all faulty circuits are implicitly simulated.
Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.)
Faster than other methods, but uses most memory.

48. Conc. Fault Sim. Example a0 b0 c0 e0 a0 b0 c0 e0 b0 d0 f1 g0 f1 d0 a e1 1 1 1 1 a 1 1 1 e b 1 c 1 1 g 1 a0 b0 c0 e0 d f 1 1 1 1 b0 d0 f1 g0 f1 d0 1 1 1

49. Fault Sampling
A randomly selected subset (sample) of faults is simulated.
Measured coverage in the sample is used to estimate fault coverage in the entire circuit.
Advantage: Saving in computing resources (CPU time and memory.)
Disadvantage: Limited data on undetected faults.

50. Motivation for Sampling
Complexity of fault simulation depends on:
Number of gates
Number of faults
Number of vectors
Complexity of fault simulation with fault sampling depends on:

51. Random Sampling Model Detected Undetected fault fault All faults with
a fixed but
unknown
coverage
Random
picking
Np = total number of faults
(population size)
C = fault coverage (unknown)
Ns = sample size
Ns << Np
c = sample coverage
(a random variable)

52. Functional vs. Structural ATPG
Automatic Test-Pattern Generation (ATPG) Basics
Functional vs. Structural ATPG

53. Carry Circuit

54. Functional vs. Structural (Continued)
Functional ATPG – generate complete set of tests for circuit input-output combinations
129 inputs, 65 outputs:
2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
No redundant adder hardware, 64 bit slices
Each with 27 faults (using fault equivalence)
At most 64 x 27 = 1728 faults (tests)
Takes s on 1 GHz ATE
Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ %

55. Automatic Test Pattern Generation: Path Sensitization
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)
sa0 1
Fault enabling 1 1 1 1 1
Fault propagation
Techniques Used: D-algorithm, Podem

56. Path Sensitization Method Circuit Example
Fault Sensitization
Fault Propagation
Line Justification

57. Using 5-Valued Logic Good Machine 1 X Failing Machine 1 X Symbol D 1 X1 X
Failing
Machine 1 X
Symbol D 1 X
Meaning
0/1
1/0
0/0
1/1
X/X
Represent two machines, which are simulated simultaneously:
Good circuit machine (1st value)
Bad circuit machine (2nd value)

58. Path Sensitization Method Circuit Example
Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 D D D D 1 D 1 1

59. Path Sensitization Method Circuit Example
Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D 1 1 D D D

60. Path Sensitization Method Circuit Example
Final try: path g – i – j – k – L – test found! D D 1 D D D 1 1

61. Irredundant Hardware and Test Patterns
Combinational ATPG can find redundant (unnecessary) hardware
Fault Test
a sa1, b sa A = 1
a sa0, b sa A = 0
Therefore, these faults are not redundant

62. Redundant Hardware and Simplification

63. Redundant Fault q sa1

64. Multiple Fault Masking
f sa0 tested when fault q sa1 not there

65. Multiple Fault Masking
f sa0 masked when fault q sa1 also present

66. Multiple Fault Masking Part II
f sa0 masked when fault q sa1 also present

67. Basic Principle of IDDQ Testing
Measure IDDQ current through Vss bus

68. Multiple IDDQ Fault Example

69. Limitations of IDDQ Testing
Sub-micron technologies have increased leakage currents
Transistor sub-threshold conduction
Harder to find IDDQ threshold separating good & bad chips
IDDQ tests work:
When average defect-induced current greater than average good IC current
Small variation in IDDQ over test sequence & between chips