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VLSI TESTING 2011 Chapter 2-1 VLSI T ESTING 積體電路測試 1 期中考範圍 PING-LIANG LAI 賴秉樑.

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Presentation on theme: "VLSI TESTING 2011 Chapter 2-1 VLSI T ESTING 積體電路測試 1 期中考範圍 PING-LIANG LAI 賴秉樑."— Presentation transcript:

1 VLSI TESTING 2011 Chapter 2-1 VLSI T ESTING 積體電路測試 1 期中考範圍 PING-LIANG LAI 賴秉樑

2 VLSI TESTING 2011 Chapter 2-2 P ING- L IANG L AI 共考 4 題,每題 25 分

3 VLSI TESTING 2011 Chapter 2-3 P ING- L IANG L AI 第一題 給定一組合電路,求出 Fault Collapsing 後的 Fault list 。

4 VLSI TESTING 2011 Chapter 2-4 P ING- L IANG L AI Fault Equivalence Rule AND gate: all s-a-0 faults are equivalent OR gate: all s-a-1 faults are equivalent NAND gate: all the input s-a-0 faults and the output s-a-1 faults are equivalent NOR gate: all input s-a-1 faults and the output s-a-0 faults are equivalent Inverter: input s-a-1and output s-a-0 are equivalent input s-a-0 and output s-a-1 are equivalent n+2 instead of 2n+2 faults need to be considered for an n-input gate. SA0 SA1 SA0 SA1 SA0 SA1 SA0 SA1 SA0 SA1 SA0 SA1 SA0

5 VLSI TESTING 2011 Chapter 2-5 P ING- L IANG L AI Fault Collapsing Summary Given F1 and F2 with T1 and T2 Equivalence – F1 is equivalent to F2 if T1 = T2 – Any test detecting F1, detects F2 and vice versa Dominance – F1 dominates F2 if T2  T1 – A test detecting F2 detects also F1 – The relation is not symmetric Input s Fault-freeFaulty Response ABC (Response)A/0B/0C/0A/1B/1C/ A B C Example: NAND2 Fault equivalence: {A/0, B/0, C/1} Fault dominance: A/1 → C/0, B/1 → C/0 Fault collapsing: {A/0, A/1, B/1}

6 VLSI TESTING 2011 Chapter 2-6 P ING- L IANG L AI An Example of Fault Collapsing A step of collapsing – {A/0, B/0, H/0} – {C/1, D/1, F/1} – {G/0, E/0, V/0} – {H/1, V/1, Z/1} – {F/0, G/1} – {F/1, G/0} – A/1 → H/1, thus A/1 can represent H/1 and all its equivalent faults in class 4 – C/0 → F/0, thus C/0 can represent F/0 and all its equivalent faults in class 5 – G/1 → V/1, thus G/1 can represent V/1 and all its equivalent faults in class 4 – H/0 → Z/0, thus H/0 belongs to equivalence class 1 – B/1 → H/1 – D/0 → F/0 – E/1 → V/1 – V/0 → Z/0 – {A/0, C/1, G/0, A/1, C/0, G/1, B/1, D/0, E/1} → Final set of fault under test A B V D C F E G Z H

7 VLSI TESTING 2011 Chapter 2-7 P ING- L IANG L AI 第二題 找出 Transistor Stuck-open 或 Stuck-short 的測試向量。

8 VLSI TESTING 2011 Chapter 2-8 P ING- L IANG L AI Transistor Faults (1/4) MOS transistor is considered as an ideal switch and two types of faults are modeled: – Stuck-open: a single transistor is permanently stuck in the open state – Stuck-short: a single transistor is permanently shorted irrespective of it's gate voltage Detection of a stuck-open fault requires a two vector sequence Transistor stuck-open fault A B C PMOS stuck-open fault Vector 1: test for A SA0 (initialization vector) Vector 2: test for A SA1 1 (Z) 0 Good circuit states Faulty circuit states

9 VLSI TESTING 2011 Chapter 2-9 P ING- L IANG L AI Transistor Faults (2/4) Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ) Transistor stuck-short fault 1 0 A B C PMOS stuck-short fault Vector 2: test for A SA0 1 (X) Good circuit output Faulty circuit output I DDQ path in faulty circuit

10 VLSI TESTING 2011 Chapter 2-10 P ING- L IANG L AI 第三題 給定一組合電路, TM 。

11 VLSI TESTING 2011 Chapter 2-11 P ING- L IANG L AI An Example of Combinational Circuit (1/3)

12 VLSI TESTING 2011 Chapter 2-12 P ING- L IANG L AI First, calculate the TM for the nodes on the second level, F, H, and G 1.CC1(F)=CC1(A)+CC1(B)+CC1(C)+1=4 2.CC0(F)=min{CC0(A), CC0(B), CC0(C)}+1=2 3.CC1(H)=min{CC0(A), CC0(B)}+1=2 4.CC0(H)=CC1(A)+CC1(B)+1=3 5.CC1(G)=CC0(C)+1=2 6.CC0(G)=CC1(C)+1=2 These TM values are then used in calculating the primary output controllability 7.CC1(Y)=min{CC1(F), CC1(H)}+1=3 8.CC0(Y)=CC0(F)+CC0(H)+1=6 9.CC1(Z)=min{CC0(H), CC0(G)}+1=3 10.CC0(Z)=CC1(H)+CC1(G)+1=5 An Example of Combinational Circuit (2/3)

13 VLSI TESTING 2011 Chapter 2-13 P ING- L IANG L AI The observability of a node indicates the effort needed to observe the logic value on the node at a primary output For second level, 11.CO Y (F)=CO(Y)+CCO(H)+1=5 12.CO Z (G)=CO(Z)+CC1(H)+1=4 13.CO Y (H)=CO(Y)+CC0(F)+1=4 14.CO Z (H)=CO(Z)+CC1(G)+1=5 For primary inputs, 15.CO Z (C)=CO Z (G)+1=[CO(Z)+CC1(H)+1]+1 =5 (line C) 16.CO Y (C)=CO Y (F)+CC1(A)+CC1(B)+1 =[CO(Y)+CC0(H)+1]+CC1(A)+CC1(B)+1=8 (line C) 17.CO YH (A)=CO Y (H)+CC1(B)+1=6 18.CO Z (A)=CO Z (H)+CC1(G)+1=8 CC1(F)=4 CC0(F)=2 CC1(H)=2 CC0(H)=3 CC1(G)=2 CC0(G)=2 CC1(Y)=3 CC0(Y)=6 CC1(Z)=3 CC0(Z)=5 An Example of Combinational Circuit (3/3)

14 VLSI TESTING 2011 Chapter 2-14 P ING- L IANG L AI 第四題 給定一循序電路,劃出 Scan DFT 的設計電路。

15 VLSI TESTING 2011 Chapter 2-15 P ING- L IANG L AI Example: Scan for Binary Counters 3-bits Counter using DFF - State table Present StateNext StateF/F Inputs ABC+A+B+CDADA DBDB DCDC As function of F(A,B,C) D A =A ⊕ BC D B =B ⊕ C D C =C’

16 VLSI TESTING 2011 Chapter 2-16 P ING- L IANG L AI Scan DFT for Binary Counters (1/2) 3-bits Binary Counters C B A 1 CLK D A =A ⊕ BC D B =B ⊕ C D C =C’ Next State and Output Combinational Logic CUT DCDC DBDB DADA

17 VLSI TESTING 2011 Chapter 2-17 P ING- L IANG L AI C B A/SO IN/SI CLK SE Scan DFT for Binary Counters (2/2)

18 VLSI TESTING 2011 Chapter 2-18 P ING- L IANG L AI QCQC 0100HH01111 QBQB ×011HHH0111 QAQA ××00LLHH001 CLK SE V 1 :PIV 2 :PI SSHCHHC V 1 :SI (PPI) V 2 :SI (PPI) C (PO) observation S: Shift operation C: Capture operation H: Hold cycle SO (PPO) observation


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