1. Virtex-6 Memory Resources Basic FPGA Architecture
Xilinx Training

2. Objectives After completing this module you will be able to…
Fully utilize the Virtex-6 distributed memory, block memory, and FIFO resources
Use the Memory Interface Generator (MIG) to build a custom memory controller for your off-chip memory component

3. Every Design Uses Memory
On-chip Block RAM and ROM
Frequently used for local data storage, shift registers, finite state machines, and FIFOs
Block RAM also includes dedicated FIFO logic
Bitstream can pre-load with fixed data for a
ROM or RAM
Distributed memory for smaller applications
External memory for larger data storage
Soft memory controllers support newest standards
Supported with the Memory Interface Generator (MIG)
Fast on-chip
memory
Virtex-6
External
memory

4. Fast Memory Interfaces
Memory Options
Distributed RAM/SRL32
On-chip BRAM
Fast Memory Interfaces
DRAM
SDRAM
DDR
DDR3
FCRAM
RLDRAM
SRAM
Sync SRAM
DDR SRAM
ZBT
QDR
FLASH
EEPROM
LOGIC
DRAM
SRAM
FLASH
EEPROM
RAM/SRL 32
BRAM
BRAM
Virtex-6
Very granular, localized memory
Minimal impact on logic routing
Great for small FIFOs
Efficient, on-chip blocks
Ideal for mid-sized buffering
Dedicated FIFO logic
Cost-effective bulk storage
Memory controller cores for
large memory requirements
Granularity
Capacity

5. Interfacing to External Memories
Supports many standards
1.5 V to 2.5 V
Single or double data rate
Different protocols
High performance
With advanced ChipSync™ technology
This is the Select I/O functionality that allows each pin to directly connect to many different I/O standards
In this case, memory specific standards improve speed
Embedded ECC logic
DDR/DDR-II/DDR3
QDR/QDR-II
RLDRAM
FCRAM
ZBT/NoBL
FIFOs
Dual-Ports
CAMs
Virtex-6
SDR SDRAM
Besides having dedicated block RAMs, these devices also have these other features that allow Xilinx FPGAs to lend themselves to memory interface applications.
Virtex-6 supports the DDR3 memory controller via a soft memory controller.

6. Distributed RAM Distributed LUT memory Logic
64-bit blocks throughout the FPGA available in 50% of the slices (Slice_M)
Single-port, dual-port, multi-port
Can be used as 32-bit shift register
Very fast (sub-nanosecond)
Ideal for small and fast memories
Coefficient storage
Small data buffers
Small state machines
Small FIFOs
Shift registers R A M
Slice3
Logic
Logic RAM
Shift Register
Logic
Not all LUTs support a distributed RAM option.
RAM

7. Distributed RAM Features
Distributed LUT memory
Can be loaded by configuration
Synchronous (clocked) write operation
But asynchronous (combinatorial) read
Can be converted to a synchronous read
when you use the associated slice flip-flop
Best built with the Core Generator
Automatically builds the input decode and output multiplexer logic
Memory can be initialized with…
Text I/O code in VHDL
Coefficient file
Or an initialization file placed in HDL code if inferring the memory R A M
Slice3
Logic
Logic RAM
Shift Register
RAM

8. Block RAM or FIFO 36K Memory Two independent ports address common data
Individual address, clock, write enable, clock enable
Independent widths for each port
Don’t forget to leave the memory disabled when not writing to avoid unpredictable results
Integrated control logic for fast and efficient FIFOs
Multiple configuration options
True dual-port, simple dual-port, single-port
Configurable aspect ratio
600-MHz operation when using data pipeline option
All operations are synchronous; all outputs are latched
Data output has an optional internal pipeline register
Integrated cascade logic
Widens/deepens FIFOs
Creates 64k x 1 from two 32k x 1 block RAMs
Byte-write enable
Enhances processor memory interfacing
Integrated 64 / 72-bit Hamming error correction
FIFO
Dual-Port
BRAM
36K Memory or
The Hamming error correction supports single and double bit error correction.

9. Segment Block RAMs Each block RAM block can be used as… or 18 Kb BRAM
FIFO or
18 Kb
BRAM /
FIFO
(1) 36 Kb BRAM OR
(1) 36 Kb or FIFO
(2) independent 18 Kb block RAMs OR
(1) 18 Kb FIFO + (1) 18 Kb block RAM

10. True Dual-Port Block RAM
True dual-port flexibility
Can perform read and write operations simultaneously and independently on port A and port B
Each port has its own clock, enable, write enable
Every write also performs a read operation
Read before write, write before read, or no change
Simultaneous read + write or write + write to the same location can cause data corruption
Make sure that address and control signals are stable
during operation
BRAM configurations
32Kx1, 16Kx2, 8Kx4, 4Kx9, 2Kx18, 1Kx36
Or two independent: 16Kx1, 8Kx2, 4Kx4, 2Kx19, 1Kx18
Each port can have its on depth x width
But FIFO always has identical read and write width
Addr A
Port A 36 36
Wdata A
Rdata A
36 Kb Memory Array
Addr B 36
Port B 36
Wdata B
Rdata B

11. Simple Dual-Port Block RAM
One read port and one write port
Natural structure for FIFOs
Allows widest implementation
72-bit data on one or both 36 Kb ports
Up to 72-bit read and write in one clock cycle
36-bit width for 18 Kb block RAM
Doubles the memory bandwidth per block
Dedicated parity bit with each block RAM
Extra bits can be used for any purpose
No dedicated parity checking logic
Read Port 72
Read Addr
Rdata A
36 Kb Memory Array
Write Addr 72
Wdata B
Write Port

12. Block RAM Configurations
Each 18K
36K
True dual-port
16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18
32Kx1, 16Kx2, 8Kx4, 4Kx9, 2Kx18, 1Kx36
Two fully independent read and write operations
Simple dual-port
16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36
16Kx2, 8Kx4, 4Kx9, 2Kx18, 1Kx36, 512x72
1 read & 1 write port
Read AND write in 1 cycle
Single-port
Read OR write in 1 cycle

13. Block RAM is Cascadable
Built-in cascade logic for 64Kx1
Cascade two vertically adjacent 32Kx1 block RAMs without using external CLB logic or compromising performance
Saves resources and improves speed of larger memories
The Core Generator enables you to easily build with the Cascade option or even larger rrays
128Kb, 256Kb, 512Kb, 1 Mb, …
Using external CLB logic for depth expansion
Not quite as fast as cascaded block RAMs
Width expansion uses parallel block RAMs DI
A[13:0]
Not Used DQ DO 1
A14
WE _ Control)
Ram_ Extension
Example: Cascade 8 block RAMs to build 256-Kb memory

14. Integrated Error Correction
Built-in optional error correction / detection
64-bit ECC (Hamming code, uses all 72 bits)
Corrects all single-bit errors
On outputs but not in the memory array
Detects, but does not correct, all double-bit errors
Identifies the address of the error
This feature is not included with Spartan-6
New feature
Deliberately insert error for testing purposes
Useful when testing external memory interfaces
64-bits +
Code
18 kbit
FIFO Logic
ECC and Interconnect

15. Byte-Wide Write Enable
Controls which byte is being written
One write enable for each byte of data and its parity bit
Useful when interfacing with processors a0
1001
ABCD
AFFD
FFFF
clk
address
data
we[3:0]
output
Byte write during write-first mode
Bytes not being written will show existing memory value on the output
Output truly reflects the new memory content
Writing always implies a read
Be careful of reading when writing
A write operation always implies a reading of data from the block RAM. Be careful reading data when writing to a block RAM.

16. FIFO 600-MHz maximum frequency
Faster than a soft implementation and saves CLBs
Full featured
Synchronous or asynchronous read and write clocks
No phase relationship is required
Full, empty, programmable almost-full/empty
Synchronous FIFO mode eliminates the uncertainty of flag latency inherent in asynchronous operation
Optional first-word-fall-through
Immediate availability of the first word after empty
FIFO configurations
Any 36-Kb block RAM: 8Kx4, 4Kx9, 2Kx18, 1Kx36, 512x72
Any 18-Kb block RAM: 4Kx4, 2Kx9, 1Kx18, 512x36
Must be same width for read and write
DIN Bus
WREN
WRCLK
RDEN
RDCLK
RESET
DOUT Bus
FULL
AFULL
EMPTY
AEMPTY
RDERR
WRERR
RDCONT<11:0>
WRDCONT<11:>
>
>
Note that the FIFO read port is port ‘A’, and the write port is port ‘B’.

17. FIFOs are Cascadable Width Cascade Depth Cascade
Flexible FIFO configuration
Expand width, depth, or both using CLB logic
Build them with the Core Generator
FIFO Generator
DIN<35:0>
FIFO #1
DOUT<35:O>
RDEN
WREN
EMPTY
DIN<71:36>
WREN
FIFO #2
DOUT<71:36>
AFULL
DIN<3:0>
FIFO #1
FIFO #2
DOUT<3:0>
512X144 FIFO
WREN
WRCLK
Width Cascade
RDCLK
RDEN
16KX4 FIFO
Depth Cascade

18. Block RAM and FIFO Capacity
Virtex-6 Device
Distr. RAM (Kb)
Block RAM/FIFO (Kb)
Block RAM/FIFO Blocks
LX75T
1,045
5,616
156
LX130T
1,740
9,504
264
LX195T
3,040
12,384
344
LX240T
3,650
14,976
416
LX365T
4,130
LX550T
6,200
22,752
632
SX315T
5,090
25,344
704
SX475T
7,640
38,304
1,064
LX2760
8,280
25,920
720

19. Two Design Flows For ISE® tool design flow (Core Generator)
Memory Interface Generator (MIG) wizard, within the CORE Generator tool
Best for all applications, except embedded applications
Simple GUI-driven tool for configuring soft memory controllers
Supports all Virtex-6 memory standards (DDR2, DDR3, QDR, RLDRAM)
For EDK design flow (Multi Port Memory Controller, MPMC)
Best for Embedded applications
Simple GUI-driven tool within the Embedded Developers Kit (EDK)
Supports same memory standards

20. Memory Interface Generator (MIG)
Customize your memory controller and interface design
Memory architecture, data rate, bus width
CAS latency, burst length
I/O bank assignments
Generates RTL source code and UCF from hardware-verified IP
Currently supported memory interfaces for Virtex-6
DDR2 SDRAM
DDR3 SDRAM
QDR II+SRAM
RLDRAM II Memory

21. MIG Design Flow Open CORE Generator™
Integrate MIG .ucf constraints to overall design constraints file
Run MIG, choose your memory parameters and generate rtl and ucf files
Import RTL and build options into ISE project
You can use the MIG to set your system and memory parameters. The tool generates the RTL and UCF files, which are the HDL code and constraints files. These files generated from a library of hardware-verified designs and your inputs are used to directly modify these files.
The RTL code provided by the MIG is not encrypted and you have the flexibility to change and customize the RTL files. If you decide to make any code changes, you should perform additional simulations to verify your results.
Synthesize design
Customize MIG design
Place and route design
Integrate/customize MIG memory RTL testbench
Timing simulation
Perform functional simulation
Verify in hardware
Optional RTL customization

22. MIG Customize your memory controller
Some options are specific to the memory controller standard
Options for the physical layer and the FPGA controller
Debug signals
IOB options for power or speed
MIG bank selection options
Displays pins required
Restricted columns are grayed out
Rules are based on IO banking, WASSO, clocking, and size of the Memory Controller
These screen shots are from the Memory Interface Generator for the DDR3 memory controller. You set the device type and the design entry flow from the CORE Generator. The MIG wizard shows the values as a reminder before setting the memory interface parameters.

23. MIG Output Files UCF folder RTL folder Simulation folder
Pinout and clocking constraints
Batch file (ise_flow.bat) with recommended build options
RTL folder
Functional modules (physical layer, user interface, controller, testbench)
Unencrypted for ease of customization
Simulation folder
HDL simulation files including memory device models Synthesis files folder
The MIG will generate these files and place them in four folders as in previous MIG versions.
The UCF file is stored along with a useful ise_flow.bat batch file. This file has the recommended implementation options for the ISE tool flow. It can be used as a guideline when you set your own ISE software options.
The second folder contains the RTL files and as you can see here from the screen shot, it has about 30 files. They are the physical layer, user interface, the controller state machine and the testbench files.
The Simulation folder contains the files necessary for the HDL simulation, including the memory device model.
Finally, a fourth folder exists that has the synthesis options recommended for those who use Synplify to run synthesis.

24. Instruction Reordering
DDR2/DDR3 controller state machine runs at half the memory clock rate
Reordering doubles the throughput of DDR2/DDR3 MC
New feature for Virtex-6 soft memory controller
Reordering controller looks ahead several commands
Reordering READs avoids the pre-charge time penalty
Execute out-of-order READs to a different bank while performing pre-charge for the current bank
Efficiency is dependent on the application (address / command patterns)
Regrouping READs and WRITEs minimizes bus turnaround
Example : Read A - Write B - Read C - Write D
Reordered to: Read A - Read C - Write B - Write D

25. DDR3 Bank Selection Guidelines
DDR3 bank assignments
Address/Control pins must be in one of the center IO columns
16-bit requires 1 data bank
32-bit requires 2 data banks
64/72-bit requires 3 data banks
Data banks must be +1/-1 rows from the Address Control bank
MIG has a bank selection GUI that incorporates all the necessary rules
Rules are explained in the User Guide
6VLX240T / 6VSX315T
Outer Column
Center Columns 17 27 37 16 26 36 15
Address 25 35 14 24 34 13 23 33 12 22 32

26. Summary Distributed LUT RAM Block RAM / FIFO
Fast, localized memories
Great for small FIFOs
Block RAM / FIFO
Bigger on-chip memories
Built-in FIFO and ECC logic
Great for mid-sized buffering
Memory controllers can be built with the MIG and the Core Generator
Fast connection to popular standard RAMs
Ideal for large memory requirements
High-Performance Block RAM
FPGA
External Memory Interfacing

27. Where Can I Learn More? User Guides Xilinx Education Services courses
Virtex-6 FPGA User Guide
Describes the complete FPGA architecture, including distributed memory, block memory and FIFO resources
Virtex-6 FPGA Memory Interface Solutions User Guide, UG406
Describes the complete library of memory controllers that can be made
Explains the rules behind the IO pin pre-optimization
Xilinx Education Services courses
Designing with the Spartan-6 and Virtex-6 Families course
Xilinx tools and architecture courses
Hardware description language courses
Basic FPGA architecture, Basic HDL Coding Techniques, and other Free videos!

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