1. 04/02/02EECS 3121 Lecture 23: DRAM + Driving large capacitances EECS 312 Reading: 10.3.3, 8.2.3, 8.5 (text)

2. 04/02/02EECS 3122 Lecture Overview Midterm 2 review Finish discussion of memories Chip packaging overview Driving large loads

3. 04/02/02EECS 3123 Midterm 2

4. 04/02/02EECS 3124 Packaging

5. 04/02/02EECS 3125 Bonding Techniques

6. 04/02/02EECS 3126 Flip-Chip Bonding

7. 04/02/02EECS 3127 Package Types

8. 04/02/02EECS 3128 Package Parameters

9. 04/02/02EECS 3129 Driving Large Capacitances

10. 04/02/02EECS 31210 Using Cascaded Buffers This ignores self-loading (junction capacitance of driving stage): derivation on page 450 of text X = CL/Cin u = tapering factor

11. 04/02/02EECS 31211 t p as a function of u and x

12. 04/02/02EECS 31212 Impact of Cascading Buffers

13. 04/02/02EECS 31213 Output Driver Design

14. 04/02/02EECS 31214 How to Design Large Transistors We don’t want a long poly run – resistive and large parasitics Place multiple narrower devices in parallel (with same gate signal)

15. 04/02/02EECS 31215 Tristate Buffers Useful for signals with multiple drivers 2 nd implementation is better in some cases b/c no series connected devices in output stage

16. 04/02/02EECS 31216 Lecture Summary Chips must be put in a package to interface with other devices Sending signals off-chip requires a lot of driving capability Driving large loads is best done using cascaded buffers with tapering factor of e