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Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 23 Lecture 23: Multistage Amps-Cascades and Cascodes Prof. Niknejad.

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Presentation on theme: "Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 23 Lecture 23: Multistage Amps-Cascades and Cascodes Prof. Niknejad."— Presentation transcript:

1 Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 23 Lecture 23: Multistage Amps-Cascades and Cascodes Prof. Niknejad

2 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Lecture Outline Example 1: Cascodes Amp Design Example 2: Two Stage CS Amp

3 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley CG Cascade: DC Biasing Two stages can have different supply currents Extreme case: I BIAS2 = 0 A

4 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley CG Cascade: Sharing a Supply First stage has no current supply of its own  its output resistance is modified

5 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley The Cascode Configuration DC bias: Two-port model: first stage has no current supply of its own Common source / common gate cascade is one version of a cascode (all have shared supplies)

6 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Cascode Two-Port Model Output resistance of first stage = Why is the cascode such an important configuration?

7 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Miller Capacitance of Input Stage Find the Miller capacitance for C gd1 Input resistance to common-gate second stage is low  gain across C gd1 is small.

8 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Port Model with Capacitors Miller capacitance:

9 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Generating Multiple DC Voltages Stack-up diode-connected MOSFETs or BJTs and run a reference current through them  pick off voltages from gates or bases as references

10 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Multistage Amplifier Design Examples Start with basic two-stage transconductance amplifier: Why do this combination?

11 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Current Supply Design Output resistance goal requires large r oc  use cascode current source

12 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Totem Pole Voltage Supply DC voltages must be set for the cascode current supply transistors M 3 and M 4, as well as the gate of M 2. Why include M 2B ?

13 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Complete Amplifier Schematic Goals: g m1 = 1 mS, R out =10 M 

14 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Device Sizes M 1 : select (W/L) 1 = 200/2 to meet specified g m1 = 1 mS  find V BIAS = 1.2 V Cascode current supply devices: select V SG = 1.5 V (W/L) 4 = (W/L) 4B = (W/L) 3 = (W/L) 3B = 64/2 M 2 : select (W/L) 2 = 50/2 to meet specified R out =10 M   find V GS2 = 1.4 V Match M 2 with diode-connected device M 2B. Assuming perfect matching and zero input voltage, what is V OUT ?

15 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Output (Voltage) Swing Maximum V OUT Minimum V OUT

16 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Port Model Find output resistance R out n = (1/20) V -1, n = (1/50) V -1 at L = 2  m  r on = (100  A / 20 V -1 ) -1 = 200 k , r op = 500 k 

17 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Voltage Transfer Curve Open-circuit voltage gain: A v = v out / v in = - g m1 R out

18 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Stage Amplifier Topology Direct DC connection: use NMOS then PMOS

19 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Current Supply Design Assume that the reference is a “sink” set by a resistor Must mirror the reference current and generate a sink for i SUP 2

20 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Use Basic Current Supplies

21 EECS 105 Fall 2003, Lecture 23Prof. A. Niknejad Department of EECS University of California, Berkeley Complete Amplifier Topology What’s missing? The device dimensions and the bias voltage and reference resistor


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