1. Floorplacement Igor L. Markov

2. Floorplacement (the term was coined by Steve Teig of Simplex/Cadence in 2002)

3. Outline Introduction Introduction Background Background Floorplanning Floorplanning Standard-cell placement Standard-cell placement Tricks & extensions Tricks & extensions Netlist pre-processing and process migration Netlist pre-processing and process migration Optimization for timing and power Optimization for timing and power Unification of placement and floorplanning Unification of placement and floorplanning Large-scale mixed-size placement Large-scale mixed-size placement Applications to large-scale floorplanning Applications to large-scale floorplanning Free-shape floorplanning Free-shape floorplanning Summary Summary

4. Traditional VLSI Design Flows Specification Logic Design Physical Design Fabrication Testing Partitioning Floorplanning Placement Routing Compaction

5. Unfortunate Trend: Interconnect Does Not Scale Source: Intel, Feb 2004 Total dynamic power breakdown for Intel Centrino ( ) Total dynamic power breakdown for Intel Centrino ( global clock included )

6. Modern VLSI Design Flows Specification Logic Design Physical Design Fabrication Testing Partitioning Floorplanning Placement Routing Physical Synthesis Design For Manufacturing Detail Routing Compaction Floorplacement This Work

7. Fixed-Die Layout 10 years ago placement was done for variable die 10 years ago placement was done for variable die Except for FPGAs Except for FPGAs Modern ASICs use pre-defined floorplans Modern ASICs use pre-defined floorplans Layout area, routing tracks, power lines, etc may be fixed before placement Layout area, routing tracks, power lines, etc may be fixed before placement Area minimization is irrelevant (area is fixed) Area minimization is irrelevant (area is fixed) New phenomenon: unroutable placements New phenomenon: unroutable placements New phenomenon: whitespace is known a priori New phenomenon: whitespace is known a priori Row utilization % = density % = 100% - whitespace % Row utilization % = density % = 100% - whitespace % Fixed-die layout is harder than variable-die Fixed-die layout is harder than variable-die Can perform variable die with fixed-die tools, but not vice versa Can perform variable die with fixed-die tools, but not vice versa Tools from Cadence, Synopsys, Mentor, IBM explicitly support fixed-die only Tools from Cadence, Synopsys, Mentor, IBM explicitly support fixed-die only

8. Review: Partitioning & Floorplanning Partitioning Partitioning Facilitates a hierarchical design methodology (older placers not scalable) Facilitates a hierarchical design methodology (older placers not scalable) Floorplanning: seeks non-overlapping locations for hard and soft blocks, shapes for soft blocks Floorplanning: seeks non-overlapping locations for hard and soft blocks, shapes for soft blocks Objectives: minimize area and wirelength Objectives: minimize area and wirelength Traditionally assumes “variable-die” (full-chip) layout Traditionally assumes “variable-die” (full-chip) layout Partitioning & Floorplanning allow early estimation of interconnect for logic optimization Partitioning & Floorplanning allow early estimation of interconnect for logic optimization

9. Std-cell DesignMixed-size DesignBlock-based Design Large rectangles can represent Large rectangles can represent Intellectual Property (IP): hard or soft Intellectual Property (IP): hard or soft Macros, memories, data-paths, analog modules Macros, memories, data-paths, analog modules Modules of unsynthesized logic Modules of unsynthesized logic

10. Placement versus Floorplanning Mathematically, placement and floorplanning (FP) are the same problem Mathematically, placement and floorplanning (FP) are the same problem Seek module locations Seek module locations Must avoid overlaps between modules Must avoid overlaps between modules Must observe region constraints Must observe region constraints Seek to minimize wirelength (power) Seek to minimize wirelength (power) Seek to satisfy delay constraints Seek to satisfy delay constraints Main differences Main differences Scale (number of objects) and algorithms Scale (number of objects) and algorithms This work: a unified tool (floorplacer) can dynamically invoke FP or placement This work: a unified tool (floorplacer) can dynamically invoke FP or placement

11. Placement vs. Floorplanning Characteristics Floor- planners Placers Floor- placers (this work) Scalable w runtime NoYesYes Scalable w wirelength NoYesYes Explicit non-overlapping constraints YesNoYes Can handle large modules YesNoYes Support for non- rectangular blocks LimitedNoYes Support for soft- rectangular blocks YesNoYes

12. Outline Introduction Introduction Background Background Floorplanning: datastructures and algorithms Floorplanning: datastructures and algorithms Standard-cell placement Standard-cell placement Tricks & extensions Tricks & extensions Netlist pre-processing and process migration Netlist pre-processing and process migration Optimization for timing and power Optimization for timing and power Unification of placement and floorplanning Unification of placement and floorplanning Large-scale mixed-size placement Large-scale mixed-size placement Applications to large-scale floorplanning Applications to large-scale floorplanning Free-shape floorplanning Free-shape floorplanning Summary Summary

13. Slicing vs. Non-slicing Floorplans Slicing FP: Simpler Non-slicing FP: More general

14. Classical Block Packing Seeks non-overlapping locations of hard and soft blocks Seeks non-overlapping locations of hard and soft blocks Objectives: minimize area and/or wirelength Objectives: minimize area and/or wirelength Core area not pre-defined (variable-die layout) Core area not pre-defined (variable-die layout) Floorplan representations: Floorplan representations: Location-based versus topological Location-based versus topological O-Tree, B*-Tree, Sequence Pair, TCG, CBL etc O-Tree, B*-Tree, Sequence Pair, TCG, CBL etc We use SP, but our methods are generally applicable We use SP, but our methods are generally applicable Simulated Annealing (SA) used for optimization Simulated Annealing (SA) used for optimization

15. Sequence Pair (SP) Proposed by Murata et al. [TCAD ’97] Proposed by Murata et al. [TCAD ’97] Two permutations of N blocks capture the geometric relation between each pair of blocks Two permutations of N blocks capture the geometric relation between each pair of blocks (, )  a is to the left of b (, )  a is above b Horizontal (Vertical) constraint graphs Horizontal (Vertical) constraint graphs Edge a  b iff a is to the left of b (a is above b) Edge a  b iff a is to the left of b (a is above b) Given block dimensions and an SP, can find locations Given block dimensions and an SP, can find locations O(n 2 )-time (faster!) O(n 2 )-time (faster!) O(n log(n))-time O(n log(n))-time O(n log(log(n)))-time O(n log(log(n)))-time A BC Left Top Right Bottom

16. Fixed Outline Floorplanning Not an area minimization problem Not an area minimization problem Rather a constraint satisfaction problem Rather a constraint satisfaction problem “Classical Floorplanning Considered Harmful” [Kahng, ISPD `00] “Classical Floorplanning Considered Harmful” [Kahng, ISPD `00] First addressed in our work [ICCD`01, TVLSI`03] First addressed in our work [ICCD`01, TVLSI`03] x-span y-span  

17. Floorplan “Slack” (compatible with many FP representations) F E D A B C F E A B C D Left Packing Right Packing x-Slack Computation <FEDBCA, ABFECD> x-slack for block A = x(A right ) – x(A left ) is the LCS

18. Example: A Slack-based Move Block with y-slack=0

19. Fixed-outline FP’er Parquet (based on Simulated Annealing) [Adya&Markov, ICCD 01, TVLSI 03] S.A. x-violation y-violation current floorplan required outline   Restart S.A.

20. Outline Introduction Introduction Background Background Floorplanning Floorplanning Standard-cell placement Standard-cell placement Tricks & extensions Tricks & extensions Pre-processing and process migration Pre-processing and process migration Optimization for timing and power Optimization for timing and power Unification of placement and floorplanning Unification of placement and floorplanning Large-scale mixed-size placement Large-scale mixed-size placement Applications to large-scale floorplanning Applications to large-scale floorplanning Free-shape floorplanning Free-shape floorplanning Summary Summary

21. Global Placement Techniques Simulated Annealing Simulated Annealing TimberWolf TimberWolf Dragon (Min-cut + SA) Dragon (Min-cut + SA) Min-cut partitioning (IBM-Cplace, Cadence-Qplace, Capo, Feng Shui) Min-cut partitioning (IBM-Cplace, Cadence-Qplace, Capo, Feng Shui) Multi-level Fiduccia-Mattheyses Multi-level Fiduccia-Mattheyses Analytical Placement Analytical Placement Force-directed [Cheng & Kuh 84] Force-directed [Cheng & Kuh 84] PROUD [Tsay & Kuh 88] PROUD [Tsay & Kuh 88] GORDIAN and GORDIAN-L [Sigl, Dohl & Johannes 91] GORDIAN and GORDIAN-L [Sigl, Dohl & Johannes 91] Geometric Partitioning [Vygen 97] Geometric Partitioning [Vygen 97] Poisson equation [Eisenmann & Johannes, DAC ‘98] Poisson equation [Eisenmann & Johannes, DAC ‘98] ACG [Alpert et al, ICCAD 2002] ACG [Alpert et al, ICCAD 2002]

22. etc. Global Placement by Recursive Min-cut Partitioning 1 2 34 Placement Bin End-case placement by branch-and-bound Placers using min-cut bisection: Capo, FengShui, IBM CPlace, Cadence QPlace Placers using min-cut bisection: Capo, FengShui, IBM CPlace, Cadence QPlace

23. Detail: Partitioning One Bin 100% area Tentative Cut-line 50%

24. Detail: Partitioning One Bin 60% 40% Shift cutline to equalize density 50%

25. Detail: Partitioning One Bin 60% 40% 60% 40% Actual cutline

26. Min-cut Placement Can Produce Slicing Floorplans Slicing Floorplan! We are going to use this effect for floorplanning We are going to use this effect for floorplanning Potential reductions in run-time and wirelength Potential reductions in run-time and wirelength Recall: traditional floorplanners use Simulated Annealing Recall: traditional floorplanners use Simulated Annealing

27. Outline Introduction Introduction Background Background Floorplanning Floorplanning Standard-cell placement Standard-cell placement Tricks & extensions Tricks & extensions Netlist pre-processing and process migration Netlist pre-processing and process migration Optimization for timing and power Optimization for timing and power Unification of placement and floorplanning Unification of placement and floorplanning Large-scale mixed-size placement Large-scale mixed-size placement Applications to large-scale floorplanning Applications to large-scale floorplanning Free-shape floorplanning Free-shape floorplanning Summary Summary

28. Whitespace Allocation vs Buffering (72K Cells, 74% WS) Min-cut/IBM WL=11.43e6 ACG/IBM WL=10.48e6 Filler Cells/Capo WL=8.76e6 Uniform WS WL=15.32e6

29. Tethering a Cell to a Location Idea: soft region constraints Idea: soft region constraints Fake nets contribute to wirelength Fake nets contribute to wirelength Penalty for violating soft region constraints Penalty for violating soft region constraints Tunable parameters Tunable parameters Size of tethering box Size of tethering box Number of cells tethered Number of cells tethered Fake Pin Fake Net

30. Tethering offers a tunable amount of freedom for further optimization Tethering offers a tunable amount of freedom for further optimization Stable Re-Placement 1. Start with an initial placement 2. Tether x% of the cells to the locations specified by initial placement Add fixed pins and fake nets Add fixed pins and fake nets 3. Rerun placement 4. Remove fake pins and nets

31. Controllable Stability of Min-cut Placers Initial5% tether0% tether Capo (randomized min-cut)

32. Application 1: Process Migration Shorter design cycles require IP reuse Shorter design cycles require IP reuse # of repeaters is increasing rapidly in more advanced technology nodes # of repeaters is increasing rapidly in more advanced technology nodes Wires are not scaling as well as devices Wires are not scaling as well as devices More # of repeaters / logic gate More # of repeaters / logic gate Different minimum local whitespace requirements for blocks during migration Different minimum local whitespace requirements for blocks during migration It is desirable to preserve relative timing characteristics of a design It is desirable to preserve relative timing characteristics of a design

33. Application 2: Floorplan Reshaping Floorplans may change due to process migration or due to poor initial estimates Floorplans may change due to process migration or due to poor initial estimates When changing the block shape, a designer may want to maintain the relative timing characteristics of the design When changing the block shape, a designer may want to maintain the relative timing characteristics of the design

34. Examples: Rescaling and Reshaping

35. Use of Netlist Pre-processing For a placed netlist For a placed netlist Geometrically rescale all locations (resulting locations may not be legal) Geometrically rescale all locations X new = X old * Width new / Width old Y new = Y old * Height new / Height old (resulting locations may not be legal) Unplace all objects, but tether them to the above “ideal” locations Unplace all objects, but tether them to the above “ideal” locations During reshaping, must re-place I/O pads During reshaping, must re-place I/O pads Perform placement, record legal locations Perform placement, record legal locations Remove fake pins and nets Remove fake pins and nets

36. Designs Used for Our Experiments Downloaded from http://www.opencores.org

37. Rescaling Results Placer: Cadence Qplace

38. Reshaping Results Placer: Cadence Qplace

39. Tricks for Performance Optimization Net-weights, net-bounds etc. extend wirelength- driven design flows to timing-driven design flows Net-weights, net-bounds etc. extend wirelength- driven design flows to timing-driven design flows Placement-driven synthesis & re-synthesis Placement-driven synthesis & re-synthesis Technology mapping, gate sizing and buffering Technology mapping, gate sizing and buffering Gate replication [Lillis et al, DAC 03 and 04] Gate replication [Lillis et al, DAC 03 and 04] DAC 04: “Efficient Timing Closure w/o Timing- driven Placement and Routing”, U. Washington DAC 04: “Efficient Timing Closure w/o Timing- driven Placement and Routing”, U. Washington DAC 04: Performance Optimization in Microarchitectural Floorplanning, GA Tech DAC 04: Performance Optimization in Microarchitectural Floorplanning, GA Tech DAC 03: Cycle-time Opt. in Floorplanning, UCLA DAC 03: Cycle-time Opt. in Floorplanning, UCLA Extended our software (Parquet) Extended our software (Parquet)

40. Tricks for Power Optimization Compute net activity factors Compute net activity factors Increase weights of active signal nets Increase weights of active signal nets Reduce the clock tree length by placing flip-flops closer together Reduce the clock tree length by placing flip-flops closer together E.g., in a given placement, cluster FFs, connect FFs in each cluster by fake nets; re-place everything E.g., in a given placement, cluster FFs, connect FFs in each cluster by fake nets; re-place everything This may increase length of signal nets This may increase length of signal nets

41. Outline Introduction Introduction Background Background Floorplanning Floorplanning Standard-cell placement Standard-cell placement Tricks & extensions Tricks & extensions Netlist pre-processing & process migration Netlist pre-processing & process migration Optimization for timing and power Optimization for timing and power Unification of placement and floorplanning Unification of placement and floorplanning Large-scale mixed-size placement Large-scale mixed-size placement Applications to large-scale floorplanning Applications to large-scale floorplanning Free-shape floorplanning Free-shape floorplanning Summary Summary

42. A New Generation of Layout Tools Place objects of very different sizes & semantics Place objects of very different sizes & semantics Standard cells Standard cells Hard and soft IP Hard and soft IP Macros and datapaths Macros and datapaths Registers and unsynthesized logic (modules) Registers and unsynthesized logic (modules) Shape modules Shape modules Discrete or variable aspect ratios Discrete or variable aspect ratios Flexible shapes (rectilinear or not) Flexible shapes (rectilinear or not) Optimize very different objectives Optimize very different objectives Handle differences between logical and physical hierarchies Handle differences between logical and physical hierarchies

43. Why Mixed-size Placement is Difficult IP reuse, memories etc  large rectangles in layout IP reuse, memories etc  large rectangles in layout Mixed-size placement is at least as hard as Mixed-size placement is at least as hard as Standard cell placement (many small movable modules) Standard cell placement (many small movable modules) Floorplanning (large, bulky modules are difficult to pack, especially on a fixed die!) Floorplanning (large, bulky modules are difficult to pack, especially on a fixed die!) Typical optimization heuristics are move-based Typical optimization heuristics are move-based Each move is “local”, i.e., affects few other objects Each move is “local”, i.e., affects few other objects However, large modules affect many other modules However, large modules affect many other modules Some moves have ripple-effect on small cells Some moves have ripple-effect on small cells Removing overlaps after global placement is not easy, invalidates top-down estimation Removing overlaps after global placement is not easy, invalidates top-down estimation

44. Cadence-recommended Mixed-size Placement Flow QPlace (SEDSM) places large modules first QPlace (SEDSM) places large modules first Designer manually removes overlaps Designer manually removes overlaps From now on, modules are considered fixed From now on, modules are considered fixed QPlace is called to place standard-cells QPlace is called to place standard-cells Otherwise, as our experiments show, Otherwise, as our experiments show, Handling many large cells is not ideal in QPlace Handling many large cells is not ideal in QPlace

45. Cadence (SEDSM/QPlace) Screenshot ( v. 5.1.67 in 2002 )

46. Cadence (SEDSM / QPlace) Screenshot ( v. 5.4.126 in 2004 )

47. Relevant Academic Work : Continuous Optimization Force directed approaches Force directed approaches [Eisenmann, Johannes, DAC ‘98] : mixed-size [Eisenmann, Johannes, DAC ‘98] : mixed-size Wires modelled as attractive forces Wires modelled as attractive forces Overlaps modelled as repelling forces Overlaps modelled as repelling forces Are good when there is abundant white-space Are good when there is abundant white-space Otherwise, designer must remove overlaps Otherwise, designer must remove overlaps

48. Relevant Academic Work : Combinatorial Optimzation Particularly promising on constrained designs Particularly promising on constrained designs [Adya & Markov, ISPD `02]: Min-cut Placement + Floorplanning [Adya & Markov, ISPD `02]: Min-cut Placement + Floorplanning [Cong et. al, ASPDAC `03]: Multi-level SA placement [Cong et. al, ASPDAC `03]: Multi-level SA placement [Adya&Markov, ICCAD `03]: Better whitespace distribution [Adya&Markov, ICCAD `03]: Better whitespace distribution [Madden et. al, ISPD `04]: Min-cut placement + Post Placement Legalization [Madden et. al, ISPD `04]: Min-cut placement + Post Placement Legalization This work : Floorplacement This work : Floorplacement

49. Capo+Parquet Flow [Adya & Markov, ISPD ’02] Proposed pre-processing techniques for solving the mixed-size placement problem Proposed pre-processing techniques for solving the mixed-size placement problem Can be used with standard-cell placers Can be used with standard-cell placers Main approach: loose integration of floorplanning and placement Main approach: loose integration of floorplanning and placement Apparently the first publication to reliably achieve overlap-free placements Apparently the first publication to reliably achieve overlap-free placements

50. Capo+Parquet Flow [Adya & Markov, ISPD ’02] (Outline) 1. Generate initial placement using a standard-cell placer (pre-processing trick) 2. Generate a fixed-outline floorplanning instance by “physical clustering” 3. Remove overlaps and generate valid macro locations using a fixed-outline floorplanner 4. Place small cells again using standard-cell placer with macros considered fixed

51. Shredding Macro Cells 012 1 2 3 0 Shred all macros into smaller sub-cells Shred all macros into smaller sub-cells Place shredded netlist using a black-box min-WL placer Place shredded netlist using a black-box min-WL placer Determine location of macros by averaging locations of sub-cells Determine location of macros by averaging locations of sub-cells (Should work with many min-WL placers) (Should work with many min-WL placers) VaVa VrVr MACRO Fake std-cell Fake wires

52. Mixed-size Flow (Capo+Parquet) [Adya&Markov, ISPD ’02] Initial PlacementFloorplanned design Final Placement

53. Shredding + Analytical Incremental Legalization [Adya&Markov, TODAES ’04] Initial PlacementFinal Placement

54. Integrated Partitioning, Floorplanning and Placement Traditional design flows apply separate optimizations Traditional design flows apply separate optimizations Mostly a scalability concern for old algorithms Mostly a scalability concern for old algorithms New generation of fast min-cut placers enable an integrated approach New generation of fast min-cut placers enable an integrated approach A min-cut partitioner is part of the placer A min-cut partitioner is part of the placer Shifting cut-lines perform floorplanning Shifting cut-lines perform floorplanning End result: locations of modules (a placement) End result: locations of modules (a placement)

55. Our New Approach: Direct Integration of Placement & Floorplanning We use top-down placement, fall back on floorplanning when necessary (many “local” calls to a floorplanner) We use top-down placement, fall back on floorplanning when necessary (many “local” calls to a floorplanner) In a mixed-size placement problem, can start with several slicing cuts In a mixed-size placement problem, can start with several slicing cuts Eventually will need to pack blocks (when exactly?) Eventually will need to pack blocks (when exactly?) This allows to solve fixed-outline floorplanning This allows to solve fixed-outline floorplanning In rare cases, packing may be infeasible (what can be done then?) In rare cases, packing may be infeasible (what can be done then?)

56. etc. Placement by Recursive Bisection + Fixed-outline floorplanning Placement bin needs Floorplanning

57. Our Floorplacement Algorithm Variables: queue of placement bins Variables: queue of placement bins Initialize: queue with top-level bin Initialize: queue with top-level bin While (queue not empty) While (queue not empty) Dequeue a bin Dequeue a bin If (bin has large/many macros) If (bin has large/many macros) Cluster std-cells into soft blocks Cluster std-cells into soft blocks Use fixed–outline floorplanner to pack all macros Use fixed–outline floorplanner to pack all macros Fix macros Fix macros else if (small enough) else if (small enough) Process end case Process end case else else Bi-partition the bin into smaller bins Bi-partition the bin into smaller bins Enqueue each child bin Enqueue each child bin

58. Floorplacement Example Cut-line (min-cut) Placement bin needs floorplanning

59. When to Floorplan ? Large-macro tests Large-macro tests At least 1 macro does not fit in child bins At least 1 macro does not fit in child bins 80% of bin area 80% of bin area What if fixed-outline floorplanning fails ? What if fixed-outline floorplanning fails ? Return to previous level of placement hierarchy Return to previous level of placement hierarchy Merge two child bins to form a parent bin Merge two child bins to form a parent bin Try area-only floorplanning Try area-only floorplanning Else final placement has overlaps (can try legalizing it at the end!) Else final placement has overlaps (can try legalizing it at the end!) Above conditions detect block-based designs, std-cell and mixed-size designs Above conditions detect block-based designs, std-cell and mixed-size designs

60. Mixed-size Placements Design A: ibm01Design B: Faraday RISC

61. Empirical Results : Placement vs. Floorplacement cktWLTimeWLTimeWLTimeWLTimeWLTime ibm013.052m2.925m3.019m3.3610m2.774.9m ibm026.839m6.511m7.4218m6.7919m5.6011m ibm1045.4635m47.568m43.686m41.0289m36.3159m ibm1565.093m66.8122m65.5192m64.99268m59.91121m ibm1851.84110m57.2158m50.7220m53,81316m50.978m Avg% - 14.88 -10.07 - 9.46 -7.720 Capo8.5+Parquet (2002) mPG (2003) Cadence SEDSM ( 2004) Capo8.8+KraftWerk (2003) Capo9.0 (Floorplacement)

62. Empirical Results: Floorplanning vs. Floorplacement GSRC Circuit #Blks Parquet (Floorplanner) Capo9.0 (Floorplacer) WL Time (sec) WL #Min-cut levels N10105.580.275.570.370 N303017.382.3516.931.891 N505020.778.1620.345.31 N10010034.5350.1232.3910.52 N20020062.28240.656.8227.43 N30030075.69433.963.6225.23

63. Floorplanning vs. Free-shape Floorplacement Rectangular shapes during floorplanning seem arbitrary Rectangular shapes during floorplanning seem arbitrary Instead, can shred blocks into fake standard cells (+fake wires) Instead, can shred blocks into fake standard cells (+fake wires) Apply traditional placement Apply traditional placement Shape blocks, minimize WL Shape blocks, minimize WL Rect- angular Free- shape CircuitParquet Shred+ Capo9.0 Avg % Ami33769874607240.1 Ami4989556046947647.5 N502022408795756.5 N10035059315754855.0

64. Summary A hybrid algorithm which combines min-cut partitioner and fixed-outline floorplanner A hybrid algorithm which combines min-cut partitioner and fixed-outline floorplanner A software tool for large-scale chip design A software tool for large-scale chip design Partitioning Partitioning Wirelength-driven floorplanning Wirelength-driven floorplanning Standard-cell and mixed-size placement Standard-cell and mixed-size placement Directly applicable to low-power design, can be adapted to performance optimization Directly applicable to low-power design, can be adapted to performance optimization DAC`03 paper from UCLA use Parquet DAC`03 paper from UCLA use Parquet User-friendly design methodologies User-friendly design methodologies Hide artifacts of algorithm development from chip designers Hide artifacts of algorithm development from chip designers

65. Another New Layout Tool Is On the Way Simultaneous placement and routing Simultaneous placement and routing Based on min-cut placement Based on min-cut placement Bypasses global routing Bypasses global routing Deals directly with detailed pre-routes Deals directly with detailed pre-routes Expected benefits Expected benefits Better overall runtime Better overall runtime More accurate estimates of wire delay More accurate estimates of wire delay More accurate estimates of congestion More accurate estimates of congestion Better end results Better end results

66. Relevant Publications: Conferences S.N. Adya, S.C. Chaturvedi, D.A. Papa and I.L. Markov, “Unification of VLSI Placement and Floorplanning", to appear at ICCAD, 2004. S.N. Adya, S.C. Chaturvedi, D.A. Papa and I.L. Markov, “Unification of VLSI Placement and Floorplanning", to appear at ICCAD, 2004. D.A. Papa, S.N. Adya and I.L. Markov, "Constructive Benchmarking for Placement", Great Lakes Symposium on VLSI (GLSVLSI), 2004. D.A. Papa, S.N. Adya and I.L. Markov, "Constructive Benchmarking for Placement", Great Lakes Symposium on VLSI (GLSVLSI), 2004. S.N. Adya, I.L. Markov and P.G. Villarrubia, ”On Whitespace and Stability in Mixed-size Placement and Physical Synthesis”, International Conference on Computer Aided Design (ICCAD), pp. 311-318, 2003. S.N. Adya, I.L. Markov and P.G. Villarrubia, ”On Whitespace and Stability in Mixed-size Placement and Physical Synthesis”, International Conference on Computer Aided Design (ICCAD), pp. 311-318, 2003. S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and P.H. Madden, "Benchmarking for Large-scale Placement and Beyond", International Symposium on Physical Design (ISPD), pp. 95-103, 2003 S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and P.H. Madden, "Benchmarking for Large-scale Placement and Beyond", International Symposium on Physical Design (ISPD), pp. 95-103, 2003 S.N. Adya, I.L. Markov and P.G. Villarrubia, "Improving Min-cut Placement for VLSI Using Analytical Techniques", IBM ACAS Conference, pp. 55-62, 2003. S.N. Adya, I.L. Markov and P.G. Villarrubia, "Improving Min-cut Placement for VLSI Using Analytical Techniques", IBM ACAS Conference, pp. 55-62, 2003. S.N. Adya and I.L. Markov, "Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell Placement", International Symposium of Physical Design (ISPD), pp.12-17, 2002. S.N. Adya and I.L. Markov, "Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell Placement", International Symposium of Physical Design (ISPD), pp.12-17, 2002. S.N. Adya and I.L. Markov, "Fixed Outline Floorplanning Through Better Local Search", International Conference of Computer Design (ICCD), pp.328-334, 2001 S.N. Adya and I.L. Markov, "Fixed Outline Floorplanning Through Better Local Search", International Conference of Computer Design (ICCD), pp.328-334, 2001

67. Relevant Publications: Journals S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and P.H. Madden, “Benchmarking for Large- scale Placement and Beyond”, IEEE Trans. on CAD, vol 23(4), April, 2004, pp. 472-487. S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and P.H. Madden, “Benchmarking for Large- scale Placement and Beyond”, IEEE Trans. on CAD, vol 23(4), April, 2004, pp. 472-487. S.N. Adya and I.L. Markov, “Combinatorial Techniques for Mixed-size Placement”, to appear in ACM Trans. on Design Automation of Electronic Systems, 2004 S.N. Adya and I.L. Markov, “Combinatorial Techniques for Mixed-size Placement”, to appear in ACM Trans. on Design Automation of Electronic Systems, 2004 S.N. Adya and I.L. Markov, “Fixed-outline Floorplanning : Enabling Hierarchical Design”, IEEE Trans. on VLSI, vol. 11(6), December 2003, pp. 1120-1135 S.N. Adya and I.L. Markov, “Fixed-outline Floorplanning : Enabling Hierarchical Design”, IEEE Trans. on VLSI, vol. 11(6), December 2003, pp. 1120-1135 S.N. Adya, I. L. Markov and P. G. Villarrubia, “On Whitespace and Stability in Physical Synthesis”, in Preparation, 2004. S.N. Adya, I. L. Markov and P. G. Villarrubia, “On Whitespace and Stability in Physical Synthesis”, in Preparation, 2004.

68. Acknowledgements Funding: GSRC (MARCO/SIA and DARPA) Funding: GSRC (MARCO/SIA and DARPA) Funding: IBM Funding: IBM Equipment grants: Intel and IBM Equipment grants: Intel and IBM Thanks for help and comments Thanks for help and comments Frank Johannes (TU Munich) Frank Johannes (TU Munich) Andrew Kahng (UCSD) Andrew Kahng (UCSD) Students: Saurabh Adya (Synplicity), Shubhyant Chaturvedi (AMD), Students: Saurabh Adya (Synplicity), Shubhyant Chaturvedi (AMD), David Papa, Jarrod Roy and Hayward Chan David Papa, Jarrod Roy and Hayward Chan

69. Thank You !