A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering.

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A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering Purdue University, West Lafayette ISPD’12

Outline Introduction Preliminaries Algorithm Experimental results Conclusion

Introduction In modern design, the sizes of transistors become smaller and smaller and usually with big macros. The placement of mixed-size designs is much more difficult than the standard-cell placement. The majority of placement algorithms utilize clustering and execute placement in a multi-level scheme. - NTUPlace3, APlace2.0, FastPlace3.0

The multi-level approach, despite being fast and scalable, has the inherent drawback of being dependent of the clustering algorithm. Abrupt changes to cell locations during the multi-level placement framework Large macros, they pose barriers and prevent cells from migrating to their natural locations. We propose a global placement algorithm that employs size scaling of circuit components to provide continuity during placement.

Preliminaries A global placement algorithm Take into account the sizes of the components and the locations of fixed macros on the chip. Only approximate locations for movable macros and cells are determined at this stage. The final locations are assigned during the legalization and detailed placement stage.

Input: a circuit net-list that represents hypergraph with vertices corresponding to the circuit components and nets corresponding to the connections among the components. Objective: minimizing the wire-length on the chip, while simultaneously eliminating cell overlapping.

(x, y): the vector of cell and movable macro coordinates WL(x, y): the wirelength of the placement SDb(x, y): the total area of movable macros and cells in bin b SDb,fixed(x, y): the total area of fixed macros inside b Wb: the width of b Hb: the height of b

Transforms formulation (1) to an unconstrained problem. solve the placement problem as a sequence of unconstrained optimization problems ( at most 50 times )

The wirelength of a net is calculated as the half-perimeter wirelength (HPWL) The objective function need to be smoothed as differentiable function so that it can be solved by analytical methods.

Algorithm Size scaling - the main global placement Optimal region approach - generate the initial placement for our global placement

Size scaling In this approach, we first scale down the dimensions of the placement components. Then, it gradually adjusts the dimensions of the components until they have reached their original sizes.

W cell : the width of the cell in the modified circuit. H cell : the height of the cell in the modified circuit. W macro : the width of the macro in the modified circuit. H macro : the height of the macro in the modified circuit. cell width,min : the width of the smallest cell in the original circuit. cell height,min : the height of the smallest cell in the original circuit. cell width,orig : the width of a cell in the original circuit. cell height,orig : the height of a cell in the original circuit. macro width,min : the width of the smallest macro in the original circuit. macro height,min : the height of the smallest macro in the original circuit. macro width,orig : the width of a macro in the original circuit. macro height,orig : the height of a macro in the original circuit.

The value of NumStep is proportional to the ratio between the area of the largest macro and the area of the smallest macro of the design. For 0 <= Step < NumStep

Each unconstrained optimization problem is solved iteratively. For the first unconstrained problem u is set to be gDPtotal(x, y): the gradient of the cell potential function. gWLtotal(x, y): the gradient of the wirelength function. The first problem have been satisfied, the algorithm uses an update scheme that halves u. The next unconstrained optimization problem of the sequence is solved with an updated u, starting from the placement solution of the previous problem.

Optimal region approach To determine an initial placement for our algorithm. For each cell or movable macro, constructing bounding boxes based on the coordinates of the pins of fixed macros that belong to the same hyperedge and excluding the location of that particular cell or movable macro. The optimal region is defined by the intersection of the median of the horizontal coordinates and the median of the vertical coordinates of the bounding boxes associated with the cell or movable macro.

(left reg, bot reg ): the coordinates of the bottom-left of the optimal region w reg (h reg ): the width (height) of the optimal region corresponding to v. RAND MAX : the maximum value returned by a pseudorandom integer rand(). rand(): range 0 to RAND MAX

Experimental results

Conclusion The placer combined size scaling with the optimal region approach as an alternative to multi-level circuit placement. Our algorithm produced high quality placement solutions for the circuits of the ISPD 2005 and ISPD 2006 mixed- size placement benchmark suites.

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