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X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang Graduate Institute of Electronics Engineering.

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Presentation on theme: "X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang Graduate Institute of Electronics Engineering."— Presentation transcript:

1 X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei, Taiwan March 20, 2007

2 2 Outline ․ Introduction ․ Previous works ․ New wire model – XHPWL ․ Applications  Min-cut partitioning placement  Analytical placement ․ Conclusion

3 3 Wiring Dominates Nanometer Design ․ As integrated circuit geometries keep shrinking, interconnect delay has become the dominant factor in determining circuit performance. Source: Cadence Design System For 90 nm technology, interconnect delay will account for 75% of the overall delay.

4 4 Solutions ․ Timing optimization techniques  Wire sizing  Buffer insertion  Gate sizing ․ New IC technologies  Copper and low-k dielectrics  X-architecture The X-architecture is a new interconnect architecture based on the pervasive use of diagonal routing in chips, and it can shorten interconnect length and thus circuit delay. X-architecture Manhattan- architecture L L

5 5 Manufacturing the X Architecture ․ X-initiative  was created to advance the usage of the X Architecture by ensuring support for the X Architecture throughout the design and manufacturing cycle. ․ Impacts on EDA tools:  Placement and Routing  Extraction

6 6 Placement and Routing for X Architecture ․ Placement  Simulated annealing Chen et al., “ Estimation of wirelength reduction forλ-geometry vs. Manhattan placement and routing ” (SLIP-2003) Over-simplified: all cells are of unit size  Partitioning placement Ono, Tilak, and Madden, “ Bisection based placement for the X architecture ” (ASP-DAC-2007) X-cutlines does not lead to shorter wirelength ․ Routing  Multilevel routing system Ho et al., “ Multilevel full-chip routing for the X-based architecture ” (DAC-2005)  Global routing Cao et al., “ DraXRouter: global routing in X-architecture with dynamic resource assignment ” (ASP-DAC-2006)

7 7 ․ Teig and Ganley, US Patent 6,848,091 ․ Ono, Talik, and Madden, ASP-DAC-2007  Study showed X-cutlines cannot reduce the X wirelength Partitioning Placement (a) Manhattan cutlines (b) X cutlines Shortest X-wirelength

8 8 Our Contributions ․ Propose a new X-half-perimeter wirelength (XHPWL) model ․ Develop effective x-architecture placers  Min-cut partitioning placement Using generalized net-weighting method  Analytical placement Smoothing XHPWL by log-sum-exp functions ․ Achieve shorter X-routing wirelength than the Manhattan HPWL model for both min-cut partitioning placement and analytical placement.

9 9 Outline ․ Introduction ․ Previous works ․ New wire model – XHPWL ․ Applications  Min-cut partitioning placement  Analytical placement ․ Conclusion

10 10 A B Manhattan Bounding Box D C A B C X Bounding Box D Half-Perimeter Wirelength (HPWL) ․ Half of the bounding box perimeter length ․ “ X bounding box (XBB) ”  The minimum region enclosing all net terminals bounded by 0, 45, 90, 135 degree lines XHPWL = ½ XBB perimeter length

11 11 (a) Compute the Manhattan Bounding Box (b) Remove the Dotted Line Segments Computing X-Half-Perimeter Wirelength (XHPWL) (c) Add the Oblique Line Segments + –

12 12 Obtain the Resulting X Bounding Box The XHPWL Function XHPWL(e) We can apply this new model to both min-cut partitioning and analytical placement algorithms.

13 13 Outline ․ Introduction ․ Previous works ․ New wire model – XHPWL ․ Applications  Min-cut partitioning placement  Analytical placement ․ Conclusion

14 14 ․ Consider a region to be divided into two subregions. ․ Find the partitioned results with the minimum wirelength  Cells are put at the center of the subregion ․ Partition recursively to obtain positions for all cells Partitioning Placement Problem c2c2 c1c1 c2c2 c1c1 Minimize wirelength (Minimize interconnect Between subregions)

15 15 Min-Cut Partitioning ․ Do not change cutlines ․ Use net-weighting during min-cut to map partitioning objective to the desired wirelength objective  Selvakkumaran and Karypis proposed to use net-weighting Technical Report, Dept CSE, UMinnesota, 2004  Chen and Chang proposed a compact form to minimize MHPWL ICCAD-2005  Roy and Markov minimizes Manhattan Steiner wirelength ISPD-2006

16 16 ․ Consider a net {v 1, v 2, …, v m, t 1, t 2, …, t n }  v i : pin in a movable cell  t i : fixed pin ․ c 1 (c 2 ) is the center of the subregion 1 (2) ․ Find the following three wirelength values  w 1 = wirelength( {c 1, t 1, t 2, …, t n } )  w 2 = wirelength( {c 2, t 1, t 2, …, t n } )  w 12 = wirelength( {c 1, c 2, t 1, t 2, …, t n } ) Generalized Net-Weighting All cells are at the left subregion. wirelength( {c 1, t 1 } ) = w 1. (a) t1t1 c2c2 c1c1 All cells are at the right subregion. wirelength( {c 2, t 1 } ) = w 2. (b) c2c2 c1c1 t1t1 Cells are at the both subregions. wirelength( {c 1, c 2, t 1 } ) = w 12. (c) c2c2 c1c1 t1t1 Region centerFixed terminalMovable cell The desired wire function wirelength( )

17 17 Partitioning Graph and Edge Weights ․ Create hypergraph G  Two fixed pseudo nodes to present the two subregions  Movable nodes to present movable cells ․ Introduce 1 or 2 hyperedges for a net  e 1 : connecting all movable nodes and the fixed pseudo node corresponding to the subregion that results in a smaller wirelength  e2: connecting all movable nodes e1e1 e2e2 c1c1 c2c2

18 18 Relation between Cut-Size and Wirelength n cut = 0 (d) e1e1 e2e2 n cut = weight(e 1 ) = |w 2 – w 1 | = w 2 – w 1 (e) e2e2 e1e1 n cut = weight(e 1 ) + weight(e 2 ) = |w 2 – w 1 | + (w 12 – max(w 1, w 2 )) = w 12 – min(w 1, w 2 ) = w 12 – w 1 (f) e1e1 e2e2 Movable node Fixed pseudo node Partition ․ Theorem: wirelength = min( w1, w2 ) + n cutsize All cells are at the left subregion. wirelength( {c 1, t 1 } ) = w 1. (a) t1t1 c2c2 c1c1 All cells are at the right subregion. wirelength( {c 2, t 1 } ) = w 2. (b) c2c2 c1c1 t1t1 Cells are at the both subregions. wirelength( {c 1, c 2, t 1 } ) = w 12. (c) c2c2 c1c1 t1t1 w 1 = w w 2 = w 1 + (w 2 – w 1 )w 12 = w 1 + (w 12 – w 1 )

19 19 Min-Cut Placement Flow Create the partitioning graph Select a bin to be partitioned Find a min-cut bisection result Add large sub-partitions into the bin list Non-empty bin list Assign net-weights using generalized net-weighting

20 20 Experiments on Min-Cut Partitioning ․ Platform: AMD Opteron 2.6GHz ․ Min-cut partitioning placer: NTUplace1 (ISPD-2005) ․ Benchmarks: IBM version 2.0 (8 circuits) ․ Three different models (for calculating w 1, w 2, w 12 )  MHPWL (Manhattan-half-perimeter wirelength)  XHPWL (X-half-perimeter wirelength)  XStWL (X Steiner wirelength) ․ Use total X Steiner wirelength to evaluate the resulting placement

21 21 Resulting Wirelengths and CPU times ․ XHPWL: 1% shorter wirelength, 8% CPU penalty ․ XStWL: 5% shorter wirelength, 22% CPU penalty Min-Cut Partitioning Total X-Steiner Wirelength (x e8) CPU Time (sec) Wire modelMHPWLXHPWLXStWLMHPWLXHPWLXStWL ibm ibm ibm ibm ibm ibm ibm ibm Average

22 22 X Steiner Wirelength Reductions ․ XHPWL reduces up to about 2% wirelength ․ XStWL reduces up to about 6% wirelength 0.00

23 23 Outline ․ Introduction ․ Previous works ․ New wire model – XHPWL ․ Applications  Min-cut partitioning placement  Analytical placement ․ Conclusion

24 24 Analytical Placement ․ Minimize W(x) + O(x)  Wire forces: dW(x) / dx  Spreading forces: dO(x) / dx Wire forces Minimize wirelengths Spreading forces Minimize overlaps W(x) wirelength function O(x) overlap function

25 25 ․ Pins on the boundary receive forces to reduce the bounding box size. A B C Wirelength Forces and the Manhattan Bounding Box D A B C Wirelength Forces and the X Bounding Box D Wire Forces in Analytical Placement B has a wire force. C and D change their force directions.

26 26 Smoothing XHPWL ․ The wire function needs to be smooth enough for analytical placement to facilitate the minimizing process ․ XHPWL is not smooth XHPWL(e)

27 27 Log-Sum-Exp Function ․ Use the log-sum-exp function to smooth the max-abs function

28 28 XHPWL-LSE Function ․ The smoothed version of the XHPWL function:

29 29 Wire Forces ․ Forces are given by the gradient of the wire function Horizontal Vertical

30 30 Minimize: α W + β O Analytical Placement Flow Find an initial placement Move cells Update α and β Spreading enough Find wire forces (dW/dx) and spreading forces (dO/dx) Cannot further minimizing

31 31 Experiments on Analytical Placement ․ Platform: AMD Opteron 2.6GHz ․ Analytical placer: NTUplace3 (ICCAD-2006) ․ Benchmarks: IBM version 2.0 (8 circuits) ․ Three different models  MHPWL (Manhattan-half-perimeter wirelength)  XHPWL (X-half-perimeter wirelength) ․ Use total X Steiner wirelength to evaluate the resulting placement

32 32 Resulting Wirelengths and CPU times ․ 3% less X-Steiner wirelength on average ․ 15% more CPU time on average Analytical Placement Total X-Steiner Wirelength (x e8) CPU Time (sec) Wire modelMHPWLXHPWLMHPWLXHPWL ibm ibm ibm ibm ibm ibm ibm ibm Average

33 33 X Steiner Wirelength Reductions ․ XHPWL can consistently reduce X-Steiner wirelengths.  Up to about 5% reduction 0.00

34 34 Outline ․ Introduction ․ Previous works ․ New wire model – XHPWL ․ Applications  Min-cut partitioning placement  Analytical placement ․ Conclusion

35 35 Summary of Wirelength Reductions Normalized Steiner Wirelength AlgorithmMin-Cut PartitioningAnalytical Placement Routing M-Arch X-Arch M-Arch X-Arch M-Arch X-Arch ibm ibm ibm ibm ibm ibm ibm ibm Average ․ Using both X placement and X routing can reduce 11% to 12% wirelength on average

36 36 Conclusions ․ The XHPWL model is effective to minimize the X- architecture wirelength ․ The generalized net-weighting method for min-cut partitioning placement can incorporate different wire models. ․ The smoothing XHPWL, XHPWL-LSE, is proposed for analytical placement ․ Using both X placement and X routing can reduce 11% to 12% wirelength on average  With only 8% to 22% CPU time penalty

37 Thank You! Resulting Placement: IBM01


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