1. On Legalization of Row-Based Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093 abk@cs.ucsd.edu CSE Department University of CA, San Diego La Jolla, CA 92093 sreda@cs.ucsd.edu Igor L. Markov EECS Department University of Michigan Ann Arbor, MI 48109 imarkov@eecs.umich.edu VLSI CAD Laboratory at UCSD

2. Outline  Introduction and Previous Work  Legalization Objectives  Legalization Method  Experimental Results  Conclusions

3. Introduction: Objectives Used in Legalization An Illegal Placement due to Overlaps  Overlap may be due: buffer insertion, gate sizing, etc  Overlap must be removed, sample objectives include minimizing: (i)Total distance moved, i.e., total perturbations (ii)Total increase in HPWL (wirelength) (iii)The maximum distance moved by a cell Overlap cell row

4. Comparisons to Previous Work  Overlap removal algos in well-known VLSI placers (separate from detail placement optimization)  Simulated annealing in TimberWolf and Dragon  Greedy cell-shifting in Capo  Network flow in GORDIAN and BonnPlace  Dynamic programming in FengShui  Additional work  Whitespace allocation via dynamic programming by Kahng, Tucker and Zelikovsky  This Work  Develop a generic dynamic-programming algorithm that optimizes one of several objectives  Study the effect of the objective choice on total wirelength and routability

5. Outline Introduction and previous work Legalization Objectives  Legalization Method  Experimental Results  Conclusions

6. Overview of the Legalization Procedure We propose a two-phase approach for overlap removal:  Phase I: Juggle cells to meet row capacity constraints.  Phase II: Remove the overlaps within each row using a generic dynamic-programming approach according to a number of objectives.

7. Phase I: Cell Juggling  Juggle cells to meet row capacity constraints by moving cells from over-capacity rows to under-capacity rows. Under- capacity rows Over- capacity rows

8. Phase I: Cell Juggling Algorithm 1.Sort the rows in a non-increasing order according to over capacity 2.For each over-capacity row r o in order: 3. Repeat until row r o is under capacity: 4. For each cell c in the row r o : find an under-capacity row r u such that moving c to r u yields the smallest increase in HPWL (wirelength) 5. Move the cell that yields the smallest increase in HPWL in Step 3.

9. Phase II: Overlap Removal Within Rows Overlap  A generic dynamic-programming technique removes all overlap while minimizing a number of objectives  Phase I outcome is a placement where the set of cells in every row meets the row capacity, but with possible overlaps.

10.  Each chain represents the possible sites that a cell can be placed at  The order of chains correspond to the order of cells from left to right in a row Overlap Removal Using Dynamic Programming sites cell 1 cell 2 cell 3 cell n row 123456789101112 start node end node

11. Start and end sites Sites that cell will be placed at Empty sites Sites not included in calculation There are many paths from the start and end nodes → select the one that optimizes one of our objectives Overlap Removal Using Dynamic Programming sites cell 1 cell 2 cell 3 cell n row 12 123456789101112

12. Min Total Distance Overlap Removal 1.Label a diagonal edge starting at some column j and chain c by the difference in distance between j and current location of cell c. 2. Label all horizontal edges by cost 0 3. Find the shortest path from start to end nodes using lexicographical sorting. row c 211023456789 12012345678

13. Min HPWL Overlap Removal row c 320100000012 23100000001 1.Label a diagonal edge starting at some column j and chain c by the difference in HPWL between placing cell c at j and its current location 2. Label all horizontal edges by cost 0 3. Find the shortest path from start to end nodes using lexicographical sorting.  This objective can be iterated (iterated minHPWL) a number of times until the percentage improvement in HPWL drops below 1% Bounding box of a net connected to c  Min HPWL has similarities to “Optimization of Linear Placements for Wirelength with Free sites,” Kahng, Tucker and Zelikovsky, ASPDAC’99.

14. 1.Label a diagonal edge starting at some column j and chain c by the difference in distance between j and current location of cell c. 2. Label all horizontal edges by cost 0 3. Find the path from start to end nodes that minimizes the maximum edge using lexicographical sort. row c 211023456789 12012345678 Min-Max Displacement Overlap Removal

15. Outline Introduction and Previous Work Legalization Objectives Legalization Method  Experimental Results  Conclusions

16. Experimental Results (IBM01) ModeOverlapsHPWLRuntime(s)Impr (%) ibm01Capo illegal9645.517- Capo legalizer 05.586- QPlace –eco05.6391.0 min HPWL05.5196.92.13% min Dist05.6231.30.28% min-max Disp05.6991.3-1.06% Iterated minHPWL 05.46239.13.14%  Improvement percentage is relative to QPlace -eco  We execute Capo (without its built-in legalizer) + Legalizer

17. ModeOverlapsHPWLRuntime(s)Impr (%) ibm02Capo illegal15021.599- Capo legalizer 01.602- QPlace –eco01.62412.0 min HPWL01.57915.22.77% min Dist01.6042.11.23% min-max Disp01.6072.21.05% Iterated minHPWL 01.56076.33.94%  Improvement percentage is relative to QPlace -eco Experimental Results (IBM02) Flow: Capo → illegal placement → Legalizer  Similar results are attained for remaining IBM benchmarks

18. Experimental Results benchmarkObjectiveHPWLGlobal Routing MetricsViolations OvertrackOvercapacity ibm01min-max disp 5.7734489375511743 min dist5.8464489375511743 minHPWL5.6254616379912602  The min dist and min-max dist objectives attempt to preserve the whitespace map → preserves routability  Min HPWL objective optimizes wirelength, but may alter the whitespace map Flow: Capo → illegal placement → Legalizer → Cadence’s WarpRoute

19. Conclusions  A generic dynamic-programming that handles a number of legalization objectives:  A two-phase legalizer is proposed  Minimum-total displacement  Minimum-total HPWL  Minimum-Max displacement  The effect of various objectives on routability and wirelength are evaluated  The effect of cut directions on the amount of overlap is studied

20. Thanks

21. Introduction: Source of Overlaps in Min-cut Placement A vertical cut on a single row can be adjusted to fit the partition size A horizontal cut cannot be adjusted to fit the partition size → overlap may occur A vertical cut on a number of subrows creates twice the number of subrows → future overlaps when horizontal cuts are executed on them 12  If a partition has more total cell weight that its capacity → overlap occurs Overlap Figure IFigure IIFigure III  Min-cut placement recursively partitions a circuit’s netlist and places the partitioned netlist in partitioned placement areas

22. Effect of Cut-Sequence on Amount of Overlaps Relationship between number of vertical cuts, total Wirelength, and number of overlaps.  Vertical cuts on a number of rows are the main reason for overlaps in min-cut placement