1. Jan. 11, '02Kim, et al., VLSI Design'021 Mutiple Faults: Modeling, Simulation and Test Yong C. Kim University of Wisconsin, Dept. of ECE, Madison, WI 53706, USA kimy@ece.wisc.edu Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974, USA va@agere.com Kewal K. Saluja University of Wisconsin, Dept. of ECE, Madison, WI 53706, USA saluja@engr.wisc.edu

2. Jan. 11, '02 Kim, et al., VLSI Design'02 2 Problem Statement  ATPG targets single stuck-at faults:  Efficient simulation and ATPG programs are available for single faults.  Some applications require a limited capability to selectively target multiple faults:  Combinational ATPG for partial scan; Kim, et al., VLSI Design’01, ITC’02.  Fault diagnosis.  Circuit optimization by redundancy removal.  Bridging faults.  Problem: To find a test for a multiple stuck-at fault using a single-fault ATPG procedure.

3. Jan. 11, '02 Kim, et al., VLSI Design'02 3 Talk Outline  Background  A single fault model for multiple faults  Applications  Combinational ATPG for acyclic sequential circuits  Exclusive test for diagnosis  Conclusion  Other applications

4. Jan. 11, '02 Kim, et al., VLSI Design'02 4 Background  Number of multiple stuck-at faults in a k line circuit is 3 k -1.  Single-fault tests are found to cover most multiple faults:  Agarwal and Fung, IEEETC’81  Hughes and McCluskey, ITC’86  Jacob and Biswas, ITC’88  Multiple-fault ATPG algorithms are not fault- oriented:  Bossen and Hong, IEEETC’71  Kohavi and Kohavi, IEEETC’72  Aboulhamid, et al., JETTA’93

5. Jan. 11, '02 Kim, et al., VLSI Design'02 5 An Obvious Fault Model  Fault is always active in the model even when it is not activated, e.g., a=1, b=0, c=0.  Some simulators and ATPG programs may not properly handle fixed logic signals. a A B C b c s-a-1 s-a-0 s-a-1 A B C a b c New PI fixed at 0

6. Jan. 11, '02 Kim, et al., VLSI Design'02 6 A New Single Fault Model  Insert a two-input in-line gate in each faulty line:  AND for s-a-0 fault  OR for s-a1 fault  Insert an AND gate with output s-a-1 fault a A B C b c s-a-1 s-a-0 s-a-1 A B C a b c

7. Jan. 11, '02 Kim, et al., VLSI Design'02 7 Proof of Correctness  Fault-free circuit:  A = a + a b c = a  B = b ( a + b + c ) = b  C = c ( a + b + c ) = c a A B C b c A B C a b c

8. Jan. 11, '02 Kim, et al., VLSI Design'02 8 Proof of Correctness  Faulty circuit:  A = a + 1 = 1  B = b. 0 = 0  C = c. 0 = 0 a A B C b c s-a-1 s-a-0 s-a-1 A B C a b c

9. Jan. 11, '02 Kim, et al., VLSI Design'02 9 Size of Model  Model of a multiple fault of multiplicity n requires at most n+3 modeling gates. a A B C b c s-a-1 s-a-0 s-a-1 A B C a b c

10. Jan. 11, '02 Kim, et al., VLSI Design'02 10 Comb. ATPG for Seq. Circuits  Single-fault tests for acyclic sequential circuits can be obtained by combinational ATPG.  Kim, et al., VLSI Design’01, ITC’01.  A combinational model is made for the sequential circuit.  About 83% of sequential circuit faults map onto single faults in the combinational model.  On an average about 17% of sequential circuit faults map onto multiple faults in the combinational model.  The method allows 100% fault efficiency.  General sequential circuits can be made acyclic by partial scan; Cheng and Agrawal, IEEETC’90.

11. Jan. 11, '02 Kim, et al., VLSI Design'02 11 An Example FF Unbalanced nodes s-a-0 FF replaced by buffer s-a-0 a b a1a1 b1b1 a0a0 b0b0 Balanced model 0 X 1 1 Combinational vector 0 1/0 1 Test sequence: 11, 0X d seq = 1 s-a-0 Multiple fault Single fault

12. Jan. 11, '02 Kim, et al., VLSI Design'02 12 Acyclic Partial-Scan ISCAS’89 Circuits:

13. Jan. 11, '02 Kim, et al., VLSI Design'02 13 Acyclic Partial-Scan ISCAS’89 Circuits: Test Generation FC: cov. (%), FE: efficiency (%), TGT: CPU s Sun Ultra 10 *Gentest for seq. and TetraMAX for comb. ATPG (Hitec produced equivalent FC, FE and TGT within 10% of Gentest)

14. Jan. 11, '02 Kim, et al., VLSI Design'02 14 Exclusive Test  Given two faults, an exclusive test detects one fault but does not detect the other.  A test for the multiple fault (f 1,f 2 ) in the following circuit is an exclusive test for f 1 and f 2 in CUT. CUT with f 1 CUT with f 2 0/1 or 1/0 Exclusive test vector

15. Jan. 11, '02 Kim, et al., VLSI Design'02 15 Diagnostic Test Example s-a-1 b c e f a d g h i Fault a 1 b 1 c 0 c 1 d 1 f 1 g 0 h 0 i 0 i 1 Test syndrome 10100 00010 00101 01010 00010 00100 00001 01000 01001 10110 Diagnostic number 5 8 20 10 8 4 16 2 18 13 a 00011 b 01100 c 10101 100% coverage Tests:

16. Jan. 11, '02 Kim, et al., VLSI Design'02 16 Exclusive Test for b 1 and d 1 b c e f a d g h i e f d g h i s-a-1 0 0 0 0/1 CUT with b 1 CUT with d 1

17. Jan. 11, '02 Kim, et al., VLSI Design'02 17 Diagnosis With Exclusive Test s-a-1 b c e f a d g h i Fault a 1 b 1 c 0 c 1 d 1 f 1 g 0 h 0 i 0 i 1 Test syndrome 101000 000101 001010 010100 000100 001000 000010 010000 010010 101101 Diagnostic number 5 40 20 10 8 4 16 2 18 45 a 000110 b 011000 c 101010 100% coverage tests and excl. test:

18. Jan. 11, '02 Kim, et al., VLSI Design'02 18 Conclusion  Single fault model allows effective use of existing single-fault ATPG and simulation tools to handle multiple fault.  Applications include:  Combinational ATPG for sequential circuits  Circuit optimization by removing multiple fault redundancies (see this paper)  Improving diagnostics by exclusive tests  Other types of tests like antitest and concurrent test (unpublished)  The modeling technique is useful for non-stuck type of faults that map onto multiple stuck-at faults, e.g., bridging faults (see this paper).