1. Sequential Testing Two choices n Make all flip-flops observable by putting them into a scan chain and using scan latches o Becomes combinational testing problem n Scan FF n LSSD n Scan hold n Leave some FF unobservable - Partial scan o General - Seq. testing is still very hard problem o Break all cycles - then complexity similar to combinational case

2. Q Q MasterSlave Data Clock Test enable data Scan data Scan Flip-Flop Scan chain Multiplexor ts+t’d Adds extra logic and delay in data paths

3. Q Q MasterSlave Scan Data Test clock Data Master clock LSSD (Level Sensitive Scan Design) Latch n Does not introduce delay in data path n Overhead is 2 ANDs and Invertor n When master clock is working, test clock is 0 and vice-versa Slave Clock Scan chain

4. Scan-Hold Flip-Flop (SHFF) n The control input HOLD keeps the output steady at previous state of flip-flop. n Applications: n Reduce power dissipation during scan n Isolate asynchronous parts during scan test n Delay testing SFF D SD TE CK HOLD Q Q To SD of next SHFF

5. Relevant Results n Theorem: A cycle-free circuit is always initializable. It is also initializable in the presence of any non-flip-flop fault. n Theorem: Any non-flip-flop fault in a cycle-free circuit can be detected by at most d seq + 1 vectors where d seq is the sequential depth of the circuit. n General ATPG complexity: To determine that a fault is untestable in a cyclic circuit, an ATPG program using nine-valued logic may have to analyze 9 N ff time-frames, where N ff is the number of flip-flops in the circuit.

6. Partial-Scan Methods Partial Scan: make only some of the flip-flops scan 1. Eliminate all cycles o Select a minimal set of flip-flops for scan to eliminate all cycles (saves area and makes it a lot easier to test). 2. Eliminate some cycles o Alternatively, to keep the overhead low only long cycles may be eliminated. o In some circuits with a large number of self- loops, all cycles except self-loops may be eliminated. It has been shown empirically that this lowers the complexity of ATPG considerably.

7. Sequential Automatic Test Pattern Generation (ATPG) Tutorial and Survey Paper: Gate-Level Test Generation for Sequential Circuits KWANG-TING CHENG University of California, Santa Barbara

8. Iterative array model Unroll FSM N time frames and treat as one combinational module

9. Five valued logic - example Values are This would imply that the fault is not testable However,… Not allowed to specify value at latch boundary

10. Nine valued logic Nine values are 0/0 0/1 0/x 1/0 1/1 1/x x/0 x/1 x/x We conclude that sequence ab = (00 01) is a test sequence To propagate the fault effect from primary input a to the output of gate g1 in time-frame 1, the only requirement is that the other input of g1 have a 0 for the fault-free circuit (there is no value requirement at this signal for the faulty circuit).

11. Finding sequentially undetectable faults Unroll the circuit a specified number of time frames Assume that the present state lines in the first time frame are fully controllable Assume that the next state lines in the last time frame are fully observable. Use combinational test pattern generator Two different procedures 1.Fault occurs only in the last time frame 2.Fault occurs in all time frames In either case, lack of combinational test implies that fault is sequentially undetectable

12. Undetectability and redundancy Redundancy is associated with I/O behavior of circuit and undetectability is associated with the test generation procedure used. A fault is called undetectable if no input sequence can produce a fault effect (D or D-bar) at any primary output A fault is redundant if the presence of the fault does not change the input/output behavior of the circuit. For a complete combinational test generator, redundancy and undetectability are equivalent. –(not so for sequential behavior)

13. Detectability under - Full-scan –Combinationally undetectable (equal to redundant) Reset –input sequence exists where the PO output responses of the good and faulty circuits differ, both starting from the reset state. Hardware reset is not available (reset sequence) –Single observation time (SOT) Sequence exists where fault effect appears at the same time and at the same output independent of the power-up state. –Multiple observations times (MOT) Sequence exists where fault effect appears, but time and place of fault effect depends on power-up state.

14. Example - SOT undetectable and MOT detectable Sequence AC = (11,01) detects fault but at different times depending on initial state of FF. –If initial state is X/0, output will be 1/0 for first vector –If initial state is X/1, output will be 1/1 for first vector and 0/1 for the second vector.

15. Sequential redundancy A fault is sequentially redundant under a mode of operation if the fault does not change the expected output sequence under that mode Modes: –Reset mode (hardware reset to a reset state) –Synchronization mode (after the reset sequence, the output sequences do not change. Can wait K cycles before looking at the outputs) –No-synchronization mode (no matter which state the machine starts in, for that state the output sequences do not change, i.e. can’t change the behavior of any state. Must hold for all sequences starting from t=0.)

16. Partial test under 1. synchronization and 2. no-synchronizations A partial test under a mode is an input sequence which distinguishes the good and faulty circuit 1.After the synchronizing sequence 2.Assuming that the good and faulty circuits power up in the same initial state. A fault is sequentially redundant (under a mode) if and only if there is no partial test.

17. Partial test (b) is STG of good machine, (c) is STG of machine with fault where cube is stuck at 0. Sequence 011 initializes good machine to 11. However faulty machine if powered up in 00 can not be initialized. Fault is partially detectable if powered up in 00, otherwise not detectable. Thus fault is partially detectable.

18. Assuming a reset state STALLION (Ma,…, STEED (Devadas,…), VERITAS (Cho, Hachtel, …) Preprocessing phase: find the set of reachable states and for each, the shortest transfer sequence from the initial state. (Veritas uses BDDs) Test generation phase: 1.Iterated array is constructed (variable number of time steps?) 2.Combinational test for array is generated first where present state is restricted to reachable states. This provides propagation sequence to a PO. 3.State transfer justification sequence is looked up from preprocessed data (how to get from initial state to test state). 4.Justification and propagation sequences derived from good machine (may not be valid for faulty machine). –Fault simulation is used to check this. If not valid, then alternate (shorter) sequence can be generated.

19. Computing reset sequences Synchronizing (reset) sequence drives the circuit to a fixed known state. (may be corrupted by fault so needs to be simulated) Deciding if a design is resetable can be done without deriving a reset sequence If resetable, reset sequence can be generated heuristically

20. Equivalence Normal notion: If a machine has a given reset state, then two machines are said to be equivalent if there reset states are equivalent (i.e. starting from these two states the I/O behavior is the same However, there may be no reset state and the machine may power up in any state. What do we mean by equivalence then?

21. Fundamental alignment theorem, Pixley[1990] Definitions: States s 1,s 2 of machines, D 1 and D 2, are: –equivalent if there is no distinguishing sequence where D 1 start in s 1, and D 2 starts in s 2. We denote this as s 1 ~ s 2. –alignable if there exists a input sequence S such that S(s 1 ) ~ S(s 2 ). Then we say that s 1  s 2 Definition: Two machines D 1 and D 2 are equivalent iff Fundamental Theorem: universal –Two machines are equivalent iff there exists a universal aligning sequence, i.e. a single sequence that aligns all pairs.

22. Proof Let where ESP is the set of equivalent state pairs. Let F(P) be an input sequence which maps at least one into ESP, i.e. Define Then Then Then aligning sequence is where and and n is where

23. Self equivalence resetA state s0 is a reset state if there exists a sequence S such that for any state s S(s) ~ s0. A design is resetable if it has a reset state. A machine may not be equivalent to itself if it is not resetable. –D1 and D2 are equivalent iff all state pairs are alignable.