1. Ultra Low Power CMOS Design Ph.D. Dissertation Proposal Kyungseok Kim ECE Auburn Univ. Chair: Prof. Vishwani D. Agrawal Committee Members: Prof. Victor P. Nelson Prof. Fa F. Dai May 11, 2010

2. 2 Outline Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion

3. 3 Energy Constrained Systems Low activity rates Relaxed speed requirements Long battery lifetimes ( more than 1 year ) Energy harvesting from the environment Examples: Micro-sensor networks, Pacemakers, RFID tags, and Portable devices Energy Harvesting Tech.Power Density ( µW/cm 2 ) Vibration - electromagnetic Vibration - piezoelectric Vibration - electrostatic Thermoelectric ( 5°C difference) Solar - direct sunlight Solar - indoor 4.0 500 3.8 60 3700 3.2 A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems. Springer, 2006.

4. 4 Subthreshold Operation (weak inversion) Eric A. Vittoz (1967) discovered that the transfer characteristics of MOS device were exponential across more than 5 decades of drain current. Measurement of a MOS transistor at very low current (Vittoz’s notebook) E. A. Vittoz, “The Electronic Watch and Low-Power Circuits,” IEEE Solid-State Circuits Newsletter, vol. 13, no. 3, pp. 7–23, 2008. S D G V gs V ds = V dd

5. 5 Minimum Operating Voltage Swanson and Meindl (1972) examined the voltage transfer characteristic (VTC) of an inverter: Minimum Voltage = 8kT/q or 200 mV at 300K ( A ring oscillator worked at 100 mV soon thereafter.) Ideal limit of the lowest possible supply voltage (2001) : Vdd = 2kT/q ≈ 57 mV at 300K R. M. Swanson and J. D. Meindl, “Ion-Implanted Complementary MOS Transistors in Low- Voltage Circuits,” IEEE JSSC, vol. 7, no. 2, April 1972. A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan, E. Nowak, I. Div, and E. Junction, “Low-power CMOS at Vdd= 4kT/q,” in Device Research Conference, 2001, pp. 22–23.

6. 6 VTC of Inverter in PTM 90nm CMOS Vth_nmos = 0.29 V, Vth_pmos = 0.21 V Nominal V DD = 1.2 V, Temp. = 300K Inverter size: W P = 5.5*L W n = 2.4*L L = 90nm SPICE simulation ( Predictive Technology Model, PTM ) gain > 1 Functional Non-functional

7. 7 Dynamic Voltage Scaling (DVS) in subthreshold region according to operating scenarios ( 128 to 1024 FFT length and 8 or 16 bit precision) Tech. : Standard 018 µm 6M CMOS (V th = 450 mV) Voltage scaling: 180 mV to 900 mV Operating Freq. : 164 Hz to 6 MHz Optimal operating point for 1024 and 16b: V dd,opt = 350 mV Freq. = 9.6 kHz E opt = 155 nJ Above-threshold low power FFT processor consumes 3.4 µJ in 0.7 µm process with 1.1 V 180 mV FFT Processor A. Wang and A. Chandrakasan, “A 180mV FFT Processor Using Subthreshold Circuit Techniques,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2004, pp. 292–529.

8. 8 Minimum Energy Operating Point Lowest energy per cycle E opt = Minimum E tot = E dyn + E leak Dynamic energy: E dyn Leakage energy : E leak E opt normally occurs in subthreshold region if speed is not constrained Speed critical operation: V dd can be higher, even above-threshold

9. 9 Dynamic Energy : E dyn = α 0→1 CV dd 2 Quadratic reduction with supply voltage V dd Activity factor α affects E dyn Leakage Energy : E leak = P leak t d = I leak V dd t d I leak is composed of subthreshod leakage, gate leakage and pn junction reverse-bias current ….. Normally smaller than dynamic energy V dd > V th

10. 10 A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold Design for Ultra Low- Power Systems. Springer, 2006. V dd < V th Dynamic Energy : E dyn scaled down as V dd 2 is comparable to E leak Leakage Energy : Assume I leak ≈ I sub,off t d exponentially increases by scaling V dd down E leak is independent of V th

11. 11 I leak and t d I o : Drain current at V gs =V th S : Subthreshold swing η : Drain-induced barrier lowering ( DIBL ) V T : Thermal voltage (=kT/q) I leak = I sub,off = I sub (V gs = 0) DIBL reduces I leak with scaling V dd K : Fitting parameter C L : Load capacitance I sub,on = I sub (V gs = V dd < V th )

12. 12 Normalized I leak and t d for INV (SPICE Simulation) E leak is mainly dominated by t d in subthreshold region.

13. 13 Total Energy per Cycle ( E tot ) 8-bit Ripple Carry Adder (PTM 90nm CMOS) with α=0.21 V dd,opt = 0.17 V E tot,min = 3.29 fJ (1.89 MHz)

14. 14 Threshold Voltage Vs. Total Energy Lowering V th does not change E opt in the subthreshold region B.H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits,” in IEEE Journal of Solid-State Circuits, Sept. 2005.

15. 15 Energy Vs. Performance Small increase of E tot in subthreshold region exponentially improves circuit speed 59.1X 14.7X 24.5X 2.7X Delay and energy per cycle of 8-bit ripple carry adder ( SPICE Simulation )

16. 16 Outline Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion

17. 17 Motivation Utilizing time slack for low power design is common in above-threshold, but not has been done in subthreshold operation Small increase in E tot can significantly improves circuit speed Two supply voltages are acceptable in today’s designs

18. 18 Dual-V dd Design Use two supply voltages V DDH and V DDL Apply V DDH to gates on critical paths to maintain performance (speed), while V DDL to gates on non-critical paths to reduce power Use level converters at interfaces of V DDL cells feeding into V DDH cells

19. 19 Driven Gates and Input Swing Level

20. 20 Gate t d and P leak in Subthreshold Level converter has unacceptable delay overhead for subthreshold circuits: Simulation data (PTM 90nm CMOS) Two supply voltages V DDH = 250 mV and V DDL = 200 mV Gate Above-threshold (V DDH =1.2V, V DDL =0.96V) Sub-threshold (V DDH =250mV, V DDL =200mV) t d (psec)P leak (nW)t d (nsec)P leak (pW) INV Level converter (LC) 9.54 68.13 6.87 31.30 0.83 254.21 46.2 214.6 LC norm. to INV7.14.6306.34.7

21. 21 Algorithm I : E opt for Single V dd Characterize Standard cells for maximum delay, average leakage, and capacitances power using SPICE simulation over subthreshold region (100 mV to 300 mV, 10 mV step, 21 points, PTM 90 nm CMOS) Low to high signal activity from logic simulator Critical delay T c from STA (21 points) Calculate E tot by the sum of energy for gates (21 points) Find lowest E tot as E opt

22. 22 Algorithm I : Results 16-bit ripple carry adder for single V dd

23. 23 Algorithm II : V DDL Assignment V DDH and T c are given as inputs from Algorithm I Use repeatedly MILP to solve E tot and V DDL assignment to selected gates on the non-critical paths to achieve minimum energy for a pair of V DDH and V DDL ( V min =90 mV ≤ V DDL < V DDH ) Find E opt and best VDDL Assignment corresponding to E opt Eliminate level converters in dual supply voltage operation by suitable constraints in MILP

24. 24 MILP for V DDL Assignment For given speed requirement T c ( V DDH ) T i is the latest arrival time at a gate i output from PI events X i Integer variable : 0 for V DDH or 1 for V DDL T. Raja, V. D. Agrawal, and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” in Proceedings of 16th International Conference on VLSI Design, Jan.2003, pp. 527–532.

25. 25 Topological Constraints Gate i Gate k Gate j XkXk XiXi XjXj HH: X j = 0 and X i = 0 → X i – X j = 0 LL: X j = 1 and X i = 1 → X i – X j = 0 HL: X j = 0 and X i = 1 → X i – X j = 1 LH: X j = 1 and X i = 0 → X i – X j = -1 X i – X j ≥ 0

26. 26 Example Result 16-bit Ripple-Carry Adder (α=0.21) in 90nm Bulk CMOS OperationV DD (V)Energy/cycle (fJ)Clock rate Nominal1.2252.21.35 GHz Minimum Energy Single V DD 0.208.712.01 MHz Dual V DD ( energy opt.)0.19, 0.136.821.57 MHz Dual V DD ( perf. opt.)0.26, 0.188.558.12 MHz

27. 27 Dual-V dd Assignment Results tctc time # of paths 16-bit ripple carry adder 22% reduction of E opt 4X4 multiplier 3% reduction of E opt

28. 28 Outline Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion

29. 29 Current Progress Validation of a dual-V dd technique in bulk CMOS subthreshold circuits A method for finding minimum energy operating point in single supply voltage An MILP for dual supply voltages in subthreshold region Level converter are avoided A paper submitted to ICCAD 2010

30. 30 Future Work Modify topological constraints to allow suitable level converters or to use circuit techniques, then possibly more V DDL cells Build MILP framework for minimum energy optimized circuit using dual-V dd and highest speed Minimum energy operating circuit immune to functional fails and process variations

31. 31 Outline Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion

32. 32 Conclusion Dual-V dd MILP framework for minimum energy operating circuit design is effective from minimum energy operating point to highest speed operation:  Ultra low power design without performance constraint  Minimum energy optimized design for given speed  Reduced energy optimization for highest speed

33. 33 Thanks!