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ELEC Digital Logic Circuits Fall 2014 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL Fall 2014, Nov 3... ELEC Lecture 6 1

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Logic Synthesis Definition: To design a logic circuit such that it meets the specifications and can be economically manufactured: Performance – meets delay specification, or has minimum delay. Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors. Power – meets power specification, or consumes minimum power. Testablility – has no redundant (untestable) logic and is easily testable. Fall 2014, Nov 3... ELEC Lecture 6 2

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Synthesis Procedure Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit. Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms: Programmable logic array (PLA) Standard cell library Field programmable gate array (FPGA) Others... Fall 2014, Nov 3... ELEC Lecture 6 3

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References on Synthesis G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, Fall 2014, Nov 3... ELEC Lecture 6 4

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Programmable Logic Array (PLA) A direct implementation of multi-output function as a two-level circuit in MOS technology. PLA styles: NAND-NAND NOR-NOR Textbook, Chapter 5. Fall 2014, Nov 3... ELEC Lecture 6 5

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Example: Two-Output Function Need four products: P1, P2, P3, P4 Fall 2014, Nov 3... ELEC Lecture 6 6 F1 A B C D F2 A B C D

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Two-Level AND-OR Implementation Also known as technology-independent circuit. Fall 2014, Nov 3... ELEC Lecture 6 7 A B C D F1 F2 P1 P2 P3 P4 INPUTSANDOR

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INPUTSNAND NAND-NAND Implementation Fall 2014, Nov 3... ELEC Lecture 6 8 A B C D F1 F2

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A NAND Gate in nMOS Technology Fall 2014, Nov 3... ELEC Lecture 6 9 VDD X Y XY GND VDD X Y XY GND VDD X Y XY GND R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, 2008, Section Depletion load Enhancement load

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NAND-NAND PLA Fall 2014, Nov 3... ELEC Lecture 6 10 ABCD F1F2 VDD GND

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NAND-NAND PLA SCHEMATIC Fall 2014, Nov 3... ELEC Lecture 6 11 ABCDF1F2 INPUTS OUTPUTS AND-plane OR-plane Transistors at cross-points

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Standard-Cell Design Obtain two-level minimized form. Map the design onto predesigned building blocks called standard cells (technology mapping). Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology: 90 nanometer CMOS 65 nanometer CMOS 45 nanometer CMOS... This is known as application-specific integrated circuit (ASIC). Fall 2014, Nov 3... ELEC Lecture 6 12

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Technology Mapping Find a common logic element, e.g., two-input NAND gate or inverter (one-input NAND). MSOP is converted into NAND-NAND circuit. Split larger input gates into two-input NAND gates and inverters. Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching). Fall 2014, Nov 3... ELEC Lecture 6 13

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A Typical Cell Library NameArea units (cost)InputsOutput function, Z Inverter2A NAND23A, B NAND34A, B, C NAND45A, B, C, D AOI214A, B, C OAI214A, B, C AOI225A, B, C, D XOR4A, B Fall 2014, Nov 3... ELEC Lecture 6 14 S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill 1994, Section 7.7, pp

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NAND3 Cell in Transistors Fall 2014, Nov 3... ELEC Lecture 6 15 ABCABC Z VDD GND

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NAND3 Cell Graphs Fall 2014, Nov 3... ELEC Lecture 6 16 Directed Acyclic Graph (DAG) (tree)

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NAND4 Cell Fall 2014, Nov 3... ELEC Lecture 6 17

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AOI21 Cell Fall 2014, Nov 3... ELEC Lecture 6 18

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OAI21 Cell Fall 2014, Nov 3... ELEC Lecture 6 19

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AOI22 Cell in Transistors Fall 2014, Nov 3... ELEC Lecture 6 20 ABCDABCD VDD GND Z Observe that in a CMOS circuit, any vector of input variables connects the output Z either to GND or to VDD, giving it a value 0 or 1, respectively. Examiningthe pull-down network, we notice that the output is connected to GND if AB = 1 or CD =1. That gives the output function as,. The cell, therefore, is AOI22.

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AOI22 Cell Fall 2014, Nov 3... ELEC Lecture 6 21

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XOR Cell Fall 2014, Nov 3... ELEC Lecture 6 22

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Technology Mapping Procedure Obtain MSOP. Convert to two-level AND-OR circuit. Transform to two-level NAND-NAND circuit. Transform to two-input NAND and inverter tree network. Perform an optimal pattern matching to obtain a minimum cost tree covering. Fall 2014, Nov 3... ELEC Lecture 6 23

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INPUTSNAND Previous Example: 2-Level NAND Fall 2014, Nov 3... ELEC Lecture 6 24 A B C D F1 F2

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A Simple Technology Mapping Fall 2014, Nov 3... ELEC Lecture 6 25 B C F1 F2 D A Cost = 24 NAND2 (3) NAND3 (4) (2) NAND2 (3)

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Circuit is a Directed Acyclic Graph (DAG) Fall 2014, Nov 3... ELEC Lecture 6 26 A B C D F1 F2 Each node is a NAND gate.

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Splitting into a Forest of Trees Fall 2014, Nov 3... ELEC Lecture 6 27 A B C D F1 F2 C B D D A

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Splitting DAG into Trees (Forest) Fall 2014, Nov 3... ELEC Lecture 6 28 A B C D F1 F2 D C B A D

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Two-Input NAND Trees Fall 2014, Nov 3... ELEC Lecture 6 29 A B C D F1 F2 C B D D A

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Alternatively, in Graph Format Fall 2014, Nov 3... ELEC Lecture 6 30 A B C D F1 F2 C B D D A

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An Improved Technology Mapping Fall 2014, Nov 3... ELEC Lecture 6 31 A B C D F1 F2 C B D D A OAI21 (4) NAND3 (4) NAND2 (3) (2) Cost = 22 Inverters inserted For pattern matching (2)

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Alternatively, in Graph Format Fall 2014, Nov 3... ELEC Lecture 6 32 A B C D F1 F2 C B D D A NAND3 (4) OAI21 (4) NAND2 (3) (2) Cost = 22 Nodes inserted For pattern matching

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Improved Technology Mapping Fall 2014, Nov 3... ELEC Lecture 6 33 B C F1 F2 D A Cost = 22 NAND2 (3) NAND3 (4) (2) NAND2 (3) AOI21 (4)

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Original Reference K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG matching,” Proc. 24th Design Automation Conf., 1987, pp Fall 2014, Nov 3... ELEC Lecture 6 34

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