Presentation on theme: "Microwave Interference Effects on Device,"— Presentation transcript:
1 Microwave Interference Effects on Device, Integrated Circuits and PC-Board SystemA Presentation on Recent ProgressN. Goldsman, Y. Bai, A. Akturk, T. Chitnis, B. Jacob, J. Baker, A. Iliadis, J. Melngailis10/10/01Effects on PC-Board and System LevelEffects on Integrated Circuit LevelEffects on Device Level
2 Standard Planar Technology Implementation: IC Chips on PC Board Chip-to-Chip Connection on PC Board:PC BoardBond PadDie (Integrated Circuits)InputOutputPinsBond WireTransmission Line
3 Chip-to-Chip Connection Bond WireBond PadPinsInputOutputICsICsTransmission Line
4 IC Chip with Bond Pads Bond Pad Die (Integrated Circuits) Electro-Static Discharge(ESD)Die(Integrated Circuits)
5 Close Shot of Bond Pad Bonding Wire Bond Pad Bond Wire Metal Insulator Si SubstrateMetalInsulatorOxideBond Wire
6 Classification of Bond Pads Analog Reference PadBi-Directional Pad with BufferGround PadInput Pad with BufferI/O PadPadless Corner PadPadless Spacer PadPad No Connect PadOutput Pad with BufferPower Pad
8 Bond Pad Parasitics - Capacitance Si SubstrateMetalInsulatorOxidePad Parasitic Capacitance vs. Process(Ref: MOSIS)Plate CapacitorMetal LayerSubstrate
9 Effects of Bond Pad Parasitics on Circuit Performance --- MatchingIC PackageDiePinBond WireBond PadBond PadBond WirePinPackage ParasiticsBond Pad(Several Hundred femto-Farad)Bond Wire & Pin(Several nano-Henry)
10 Effects of Bond Pad Parasitics on Circuit Performance --- MatchingChip-to-Chip Connection on PC BoardTransmission LineBond WireBond PadPins
11 Effects of Bond Pad Parasitics on Circuit Performance --- MatchingInputOutputIC 1IC 2Transmission LineInputOutputIC 1IC 2
12 Effects of Bond Pad Parasitics on Circuit Performance --- MatchingWhy to Match?Maximize Power TransformationEliminate ReflectionMatch impedance on board with bond pads, bond wire and pins:IC 1IC 2InputOutputTransmission LineTune to Z0Tune to Z0Tune to Z0Z0If Impedances are not matched, signals will get reflected.
13 CMOS Low Noise Amplifier IC1 Input Circuit Inductor L1 and capacitors C1 and C2 are on – chip components for input matching.Inductor L2 is the downbond inductor and is also used in input matching.In addition to the shown components the pad capacitance and package model were taken into consideration.
14 Matching Real part Looking into the MOSFET M1, input impedance The real part is made to be 50 Ohms.Inductors L1 and C1 give additional degrees of freedom to have the input resonate at 2.4 GHzValues are tuned to include effects of pad and package parasiticsModels provided by the foundry were used for on-chip inductors and capacitors.Real part
15 Transistor sizingSizing is an important factor in the Power consumed vs. Noise Figure trade off. The expression below is derived by constraining the power consumed and then optimizing the Noise Figure.Substituting appropriate values gives a transistor size of W = 200 microns. = Operating frequencyL = Device LengthRs = Source Resistance
17 Simulation Results Simulation results Operating at 2.4 GHz Power gain = 21 dBNoise Figure = 2.7 dBSupply voltage = 2.5VIdc = 7.5 mAThis is a test chip.Results are obtained for an output termination of 50 Ohms
18 Effects of Bond Pad Parasitics on Circuit Performance --- MatchingExample Circuit: RF Power AmplifierBond Pad, Bond Wire, and PinBond Pad, Bond Wire, and PinPA without bond pads or package parasiticsPA with bond pads and package parasiticsBond pad, bond wire, and pin add together which shift the resonant frequency, decrease the power gain, and narrow the bandwidth of the amplifier.
19 Device Switching Details Performance Improves by the reduction of the capacitive loadthe utilization of the halo implants
21 solved for each mesh point Governing Equations<=Device Equations aresolved for each mesh point/ <=\Supplementary deviceequations=>=>SupplementaryLumped circuitequation
22 Example Solutions of the Previous Equations Potential Distribution:The applied voltage at the gate is shared between the oxide and thesurface after the built-in voltages are deducted.More electrons are attracted to the channel as VGS gets higher. Thisalso drags the surface potential to a higher levelAs the gate voltage increases, the surface potential does not increaselinearly, causing the vertical electrical field to take higher values. Thismight eventually lead to a breakdown, around 3MV/cmCarrier Distribution:To turn the device on, the minority carriers are attracted to the oxideinterface, ultimately they invert the surface and form a conductive channel,by the application of a positive VGS for electrons and negative for holesWhen the device is turned on, the accumulation of the carriers at the interfaceforms the conductive path
23 Potential Distribution for VGS=1V and VGS=5V VDS=1.5V and VSB=0V VGS=1V EOX_MAX=3MV/cm VGS=5V EOX_MAX=15MV/cm
24 Electron Concentration of NMOS throughout the substrate, specifically around the interface, when the channel is on and offOffOnThe bump shows theattracted carriers
25 Hole Concentration of PMOS throughout the substrate, specifically around the interface, when the channel is on and offOnOffThe bump shows theattracted carriers