1. Microwave Interference Effects on Device,
Integrated Circuits and PC-Board System
A Presentation on Recent Progress
N. Goldsman, Y. Bai, A. Akturk, T. Chitnis, B. Jacob, J. Baker, A. Iliadis, J. Melngailis
10/10/01
Effects on PC-Board and System Level
Effects on Integrated Circuit Level
Effects on Device Level

2. Standard Planar Technology Implementation: IC Chips on PC Board
Chip-to-Chip Connection on PC Board:
PC Board
Bond Pad
Die (Integrated Circuits)
Input
Output
Pins
Bond Wire
Transmission Line

3. Chip-to-Chip Connection
Bond Wire
Bond Pad
Pins
Input
Output
ICs
ICs
Transmission Line

4. IC Chip with Bond Pads Bond Pad Die (Integrated Circuits)
Electro-Static Discharge
(ESD)
Die
(Integrated Circuits)

5. Close Shot of Bond Pad Bonding Wire Bond Pad Bond Wire Metal Insulator
Si Substrate
Metal
Insulator
Oxide
Bond Wire

6. Classification of Bond Pads
Analog Reference Pad
Bi-Directional Pad with Buffer
Ground Pad
Input Pad with Buffer
I/O Pad
Padless Corner Pad
Padless Spacer Pad
Pad No Connect Pad
Output Pad with Buffer
Power Pad

7. --- Eliminate Harmful Static Charge
ESD Pad
--- Eliminate Harmful Static Charge
Example I/O ESD Pad:
ESD Transistor PMOS
Pad Logic
ESD Transistor NMOS
Bond Pad
Layout
Schematic

8. Bond Pad Parasitics - Capacitance
Si Substrate
Metal
Insulator
Oxide
Pad Parasitic Capacitance vs. Process
(Ref: MOSIS)
Plate Capacitor
Metal Layer
Substrate

9. Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
IC Package
Die
Pin
Bond Wire
Bond Pad
Bond Pad
Bond Wire
Pin
Package Parasitics
Bond Pad
(Several Hundred femto-Farad)
Bond Wire & Pin
(Several nano-Henry)

10. Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Chip-to-Chip Connection on PC Board
Transmission Line
Bond Wire
Bond Pad
Pins

11. Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Input
Output
IC 1
IC 2
Transmission Line
Input
Output
IC 1
IC 2

12. Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Why to Match?
Maximize Power Transformation
Eliminate Reflection
Match impedance on board with bond pads, bond wire and pins:
IC 1
IC 2
Input
Output
Transmission Line
Tune to Z0
Tune to Z0
Tune to Z0 Z0
If Impedances are not matched, signals will get reflected.

13. CMOS Low Noise Amplifier IC1 Input Circuit
Inductor L1 and capacitors C1 and C2 are on – chip components for input matching.
Inductor L2 is the downbond inductor and is also used in input matching.
In addition to the shown components the pad capacitance and package model were taken into consideration.

14. Matching Real part Looking into the MOSFET M1, input impedance
The real part is made to be 50 Ohms.
Inductors L1 and C1 give additional degrees of freedom to have the input resonate at 2.4 GHz
Values are tuned to include effects of pad and package parasitics
Models provided by the foundry were used for on-chip inductors and capacitors.
Real part

15. Transistor sizing
Sizing is an important factor in the Power consumed vs. Noise Figure trade off. The expression below is derived by constraining the power consumed and then optimizing the Noise Figure.
Substituting appropriate values gives a transistor size of W = 200 microns.
 = Operating frequency
L = Device Length
Rs = Source Resistance

16. CMOS LNA Layout
Input_C1
Input_L1
MOSFETs
Output_C2

17. Simulation Results Simulation results Operating at 2.4 GHz
Power gain = 21 dB
Noise Figure = 2.7 dB
Supply voltage = 2.5V
Idc = 7.5 mA
This is a test chip.
Results are obtained for an output termination of 50 Ohms

18. Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Example Circuit: RF Power Amplifier
Bond Pad, Bond Wire, and Pin
Bond Pad, Bond Wire, and Pin
PA without bond pads or package parasitics
PA with bond pads and package parasitics
Bond pad, bond wire, and pin add together which shift the resonant frequency, decrease the power gain, and narrow the bandwidth of the amplifier.

19. Device Switching Details Performance Improves by
the reduction of the capacitive load
the utilization of the halo implants

20. General Device Hierarchy
=>
=>
=>

21. solved for each mesh point
Governing Equations
<=
Device Equations are
solved for each mesh point
/ <= \
Supplementary device
equations
=>
=>
Supplementary
Lumped circuit
equation

22. Example Solutions of the Previous Equations
Potential Distribution:
The applied voltage at the gate is shared between the oxide and the
surface after the built-in voltages are deducted.
More electrons are attracted to the channel as VGS gets higher. This
also drags the surface potential to a higher level
As the gate voltage increases, the surface potential does not increase
linearly, causing the vertical electrical field to take higher values. This
might eventually lead to a breakdown, around 3MV/cm
Carrier Distribution:
To turn the device on, the minority carriers are attracted to the oxide
interface, ultimately they invert the surface and form a conductive channel,
by the application of a positive VGS for electrons and negative for holes
When the device is turned on, the accumulation of the carriers at the interface
forms the conductive path

23. Potential Distribution for VGS=1V and VGS=5V VDS=1.5V and VSB=0V
VGS=1V EOX_MAX=3MV/cm VGS=5V EOX_MAX=15MV/cm

24. Electron Concentration of NMOS throughout the substrate, specifically around the interface, when the channel is on and off
Off On
The bump shows the
attracted carriers

25. Hole Concentration of PMOS throughout the substrate, specifically around the interface, when the channel is on and off On
Off
The bump shows the
attracted carriers