1. ITRS-2001 Design ITWG Plan December 6, 2000 Bill Joyner, SRC/IBM

2. Role of Design in ITRS Before 1999 –Focused on hardware design and test: tool issues and technologies –Detached from rest of Roadmap 1999 –Highlighted SOC trends and requirements –Better integration, interaction with other ITWGs 2001 and Beyond –Much more involvement in crosscut issues with other ITWGs E.g., panel on interconnect systems and optimization; chip size; cost;... Bidirectional interactions with other ITWGs –Consideration of new and important areas: Applications Architectures Optimized uses of process technology Analog/mixed signal and other technologies

3. Goal: “Living Roadmap” Transparent, self-consistent Roadmap –Documentation of “algorithmic” relationships within, between different parts of the Roadmap –Some relationships or derivations inherently difficult to capture, e.g., Max Litho Field Size derivation -- but these can be “hard-wired” Sanity checks (e.g., cost or power), “which rule does not belong” checks, etc. Easier calibration, adjustment to actual design or technology data points Initial focus: ORTCs Interactions with other ITWGs, panels (chip size, etc.)

4. Living Roadmap Framework GSRC Technology Extrapolation (GTX) Engine http://vlsicad.cs.ucla.edu/GSRC/GTX Open source, allows flexible capture and study of impact of modeling choices, optimization constraints

5. System Drivers Chapter Proposal Proposal: Evolve from SOC Chapter in 1999 ITRS Rationale –“SOC” is too specific; ITRS should not perpetually contain such a chapter –Terms such as ASIC, MPU (with all their flavors) are not well-defined in the ITRS front material –Should set context: “what is consuming the silicon?” with as concrete definitions as possible (replace SOC chapter, after ORTC / before Design) Four driver classes (proposed) –Analog/RF/MEMS –ASIC = compiled HDL  gates –High-volume custom = uP, DSP, embedded memories, reprogrammable –SOC = high integration, low cost, low TTM Design ITWG would drive, collaborate with other ITWGs Under consideration by Roadmap Committee

6. Design Chapter Organization - Issues Few if any metrics –Poor history of metrics for design technology –We believe that cost issues, and Design as part of NRE cost, are strongly influencing the landscape of the semiconductor industry -- where is this in the ITRS ? “Too many axes” –Challenges: driven by Silicon, System, Design Process complexities –Issues vs. Challenges vs. Needs vs. Solutions (Challenges >> Needs >> Issues ?) (“consider it” << “need it” << “it’s a hard problem” ?) –Application domains: high-volume custom, ASIC, AMS/RF/MEMS, SOC –Long-term vs. Short-Term –Level of abstraction / design level: System, logic, circuit, physical, manufacturing interface Spec, RTL/code, gates/cells, masks, chip –Synthesis (creation) vs. Analysis (validation) –Criticality (rank-ordering of issues)

7. Design Chapter Organization - Proposal “Context” –Scope of Design Technology –High-level summary of complexities (at level of “issues”) Silicon trends/effects (include ORTC lines ) System complexity (drivers/architectures = what is being designed) Methodology evolution –Cost, productivity, quality, and other metrics of Design Technology Overview of Needs –System Driver classes and associated emphases –Resulting needs (e.g., power, reprogrammability, cost-driven design) Summary of Difficult Challenges – by Driver Class –Difficult Challenges Tables (visualize as many axes as possible) Detailed Statements of Needs and Potential Solutions –System-Level Synthesis, Logic+Physical+Circuits, Functional Verification, Test, Design Process –Metrics included; separate tables optional

8. Design Chapter Organization - Proposal Five areas of Design Design Process Infrastructure, design process metrics, … System-Level Design Designing the system Infrastructure for design IP reuse Functional Verification System-level, RT-level, … Logical-Physical-Circuits Circuits includes “DSM effects”, hard-IP reuse/migration, etc. Test

9. Table: Specific Design Challenges for High-Volume Custom Drivers near-term (>100nm) long-term (<100nm) criticality Design Process System-Level Design Functional Verification Logic/Phys/ Circuits Test Proposal: have one of these tables for every Design Driver class system only challenge #1 cross-cutting challenge between logic and system#1 cross-cutting challenge between systems, logic, circuit, PD, and system system only challenge #1 Logic only challenge #1 system only challenge #1 circuit only challenge #1 system only challenge #1

10. Core Figures and Tables - 2001 Table – Issues taxonomy Table – Metrics of Design Technology Figure – Evolution of Design System Architecture Figure – “Business Design Driver” Classes Table(s) – Design Difficult Challenges –Should this Table, or Tables, look like previous slide ? Additional Figures, Tables within the Detailed Statements of Needs and Potential Solutions sections –e.g., Power, SOC Design Productivity,...

11. Scenario: major increase in SOC memory content forced by insufficient design, reuse productivity increases (Japan) ITRS meeting, San Francisco, 2000

12. SOC Low Power Total Power Trend with No Low Power Solution Total Power Trend with Low Power Solution Scenario to keep 3W Low Power ITRS, meeting in Leuven

13. Shopping List from Other ITWGs Design cost data (mostly sought from People, not ITWGs) –Both custom and semi-custom chips –Is design cost / chip constant ? design cost / xtor ? –How about #people or time needed to complete a design ? Impasse with, e.g., clock frequency projections for ORTCs (this is how Mark Horowitz thinks...) –inverter speed: speed of inverter driving cap load = 4x input cap –Idsat, Cox -- and what corners these were derived for –assumed threshold and supply voltages –controllability of Vt (and other manufacturing tolerances of interest) –change in device behavior with temperature Inputs re architectural models for Design Driver classes

14. Design ITWG Schedule (Tentative) U.S. Design DTWG - initial draft responsibility Design ITWG - meeting December 12 IEDM U.S. Design DTWG - teleconf December 13 First drafts of new text: January 31 ? Meeting (ITWG, DTWG) in February (e.g., ISSCC Feb 5-7) What is the overall ITRS-2001 schedule ?