Presentation on theme: "JEDEC Standards -Nicole Okamoto and Widah Saied"— Presentation transcript:
1 JEDEC Standards -Nicole Okamoto and Widah Saied All figures from Jedec Standard JESD51-12
2 JEDEC IntroductionJEDEC was founded in 1960 and stands for the Joint Electron Device Engineering Council.JEDEC is the standardization body of the Electronic Industries Alliance, which helps develop standards on electronic components, consumer electronics, electronic information, telecommunications, and internet security.JEDEC issues often used standards for device interfaces, such as RAM and DDR SDRAM(double-data-rate synchronous dynamic random access memory), which is a type of memory in integrated circuits used in computers.Wikipedia,
3 JEDEC IntroductionJEDEC Philosophy:JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products.JEDEC has 2700 participants, appointed by 270 companies work in 50 committees. The world community accepts the publications and standards that they generate.Jedec,
4 Examples of standardsJESD 22-A103C HIGH TEMPERATURE STORAGE LIFE: The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices.High Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devicesDuring the test elevated temperatures (accelerated test conditions) are used without electrical stress applied.
5 Examples of standardsJESD 22-A104C TEMPERATURE CYCLING: This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling.JESD 22-A106B THERMAL SHOCK: This test is conducted to determine the resistance of a part to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes.
6 JESD 51 Methodology for the Thermal Measurement of Component Packages JESD51-1 Integrated Circuit Thermal Measurement Method – Electrical Test MethodJESD51-2 Integrated Circuit Thermal Test Method Environmental Conditions – Natural ConvectionJESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount PackagesJESD51-4 Thermal Test Chip GuidelineJESD51-5 Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment MechanismsJESD51-6 Integrated Circuit Thermal Test Method Environmental Conditions – Forced ConvectionJESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
7 JESD 51 cont.JESD51-8 Integrated Circuit Thermal Test Method Environmental Conditions – Junction to BoardJESD51-9 Test Boards for Area Array Surface Mount Package Thermal MeasurementsJESD51-10 Test Boards for Through-Hole Perimeter Leaded Package Thermal MeasurementsJESD51-11 Test Boards for Through-Hole Area Array Leaded Package Thermal MeasurementsJESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information
9 JESD 22-A103C High Temperature Storage Life Scope: Determine the effect of time and temperature, under storage conditions, of thermally activated failure mechanisms of solid state electronic devices.Jedec Standard,
10 Apparatus of TestThe apparatus is a temperature controlled chamber capable of maintaining the entire sample population at a specified testing temperature.
11 Method of TestingThe samples will be stored at one of the temperature conditions given in Table 1:Table 1: High Temperature Storage ConditionsCondition A: +125(-0/+10) ºCCondition B: +150(-0/+10) ºCCondition C: +175(-0/+10) ºCCondition D: +200(-0/+10) ºCCondition E: +250(-0/+10) ºCCondition F: +300(-0/+10) ºCCondition G: +85(-0/+10) ºC
12 Method of TestingTypically, the sample is tested under condition B for 1000 hours, but other conditions or durations may be used.Note: the rate of temperature increase should be low to prevent overstress of the sample that would not occur under normal conditions.The failure criteria for a sample is:The part can no longer function as designedCracking, chipping, or breaking of the package as long as the package performance was critical to the performance of the sample. However, if the damage was due to fixtures or handling, then failure is not attributed to the test.
13 Method of Testing Things to be specified: Sample size and number of failuresTime and conditionsWhether intermediate measurements were taken
14 JESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information qJA junction-to-still ambient air resistance (natural convectionqJMA junction-to-moving air resistance (forced convection)
16 Deviations During Application Results during application may vary since the application may differ from the following test conditions:Power dissipationAir velocity, direction, turbulencePower and number of adjacent components and boardsPCB orientation and sizeTwo-sided vs. one-sided mountingDie sizeCopper trace thickness and widthsEnvironment (for example, natural convection tests are done in a chamber 1 ft3)
17 Conduction resistances qjctop, qjcbot – junction to top of case and bottom of case resistances, respectivelyqjb – junction to board resistancesLeaded package: measure Tboard to foot of leadSurface mount package: measure board trace within 1 mm of packageThese resistances are found by forcing all of the heat flow to go out the respective surface, which may not match reality
18 Thermal Characterization Parameter ΨJT – junction to top thermal characterizationΨJB – junction to board thermal characterizationThe equations are the same as those for thermal resistance q except that the power P is now the total power, not just the power in that direction. For example, if only 5% of your total heat loss is down through the PCB, your P would still be your total power.These can help with estimates of junction temperature for object already under use where temperatures can be measured and there is no heat sink present (instead of for the design phase)
19 Compact ModelsTwo-resistor model: good for hand calculations but not really accurate
20 DELPHI Compact ModelsThese are mathematical models, not thermal resistance modelProvided by some component manufacturers
21 Effect of Package Construction on Thermal Results 2s0p: two signal planes, zero power planes on laminate substrate for plastic ball grid array packagesAdded copper improves performance
22 Effect of PCB DesignMore copper to spread heat means better performance.
29 ReferenceJedec the Standards Resource for the World Semiconductor Industry (October 2006). .Jedec Standard JESD 22-A103C High Temperature Storage Temperature . Retrieved OctoberJedec Standard JESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information. Retreived OctoberWikipedia the Free Encyclopedia(October 2006). Jedec. Retrieved October