1. Efficient Reachability Checking using Sequential SAT G. Parthasarathy, M. K. Iyer, K.-T.Cheng, Li. C. Wang Department of ECE University of California – Santa Barbara

2. Motivation Satisfiability in sequential circuits very important Satisfiability in sequential circuits very important Applications to Reachability Analysis, model checking and ATPG Applications to Reachability Analysis, model checking and ATPG Seen resurgence in SAT with recent advances Seen resurgence in SAT with recent advances –C-SAT, BerkMin, Zchaff, Grasp, etc.. Similar performance benefits can be derived for search in a sequential space Similar performance benefits can be derived for search in a sequential space Sequential SAT has been proposed Sequential SAT has been proposed –How does this perform versus current methods for reachability checking ?

3. Outline Sequential SAT Sequential SAT Search Strategies in Sequential SAT Search Strategies in Sequential SAT Efficient State Caching Efficient State Caching Reachability Checking with sequential SAT Reachability Checking with sequential SAT Experimental Results Experimental Results –Comparison with BDDs –Comparison with BMC Conclusions Conclusions

4. ATPG Formulation of Circuit Justification Typically X-Path based Typically X-Path based Decision points are subset of Primary inputs and internal signals eg. FAN’s headlines Decision points are subset of Primary inputs and internal signals eg. FAN’s headlines Nodes on justification frontier are justified one-by-one Nodes on justification frontier are justified one-by-one a b c d e = 0 J-frontier = {e} Select J-node: e Satisfy J-node: 1 st x-path{c,a}; select a = 0; Implications: c=0, d=1, e=0; J-node satisfied Is J-frontier empty: yes; DONE: Solution {a,b} = {0,X} X-path J-frontier

5. The Most Effective SAT Solvers Backtrack search Backtrack search Boolean constraint propagation Boolean constraint propagation “Reasonable” branching heuristic “Reasonable” branching heuristic Clause recording Clause recording –Non-chronological backtracking Search strategies Search strategies –Restarts / Random backtracking Efficient data structures Efficient data structures –E.g. head/tail lists; watched literals; literal sifting Examples: BerkMin; Chaff; SATO; rel_sat; GRASP Examples: BerkMin; Chaff; SATO; rel_sat; GRASP

6. Structural Search v/s Pure SAT FeatureSATStructuralAdvantage 1 Conflict-based Learning YesMinimalSAT 2 Eff. Implications YesNoSAT 3 Structural Information MinYesStructural 4 Algorithm Complexity LowHighSAT 5 Decision Ordering HeuristicProb Struct/SAT (sat/unsat) 6 Size of SAT Assignments HighLowStructural Iyer et. al., SATORI – A Fast sequential SAT solver for circuits, ICCAD 2003 Iyer et. al., SATORI – A Fast sequential SAT solver for circuits, ICCAD 2003

7. Sequential SAT – S ATORI Based on implicit time frame (TF) expansion Based on implicit time frame (TF) expansion For each TF, a combinational solver is used to find a solution For each TF, a combinational solver is used to find a solution –includes heuristics to minimize the number of state variables with value assignment using 3-valued logic –Maximize size of these sets The “state” part of solution further justified in prior TF The “state” part of solution further justified in prior TF A conflict clause corresponding to the “state” part of the solution is added A conflict clause corresponding to the “state” part of the solution is added –Prevents reaching the same state again in search Efficient state caching and retrieval Efficient state caching and retrieval Is complete Is complete –Given enough time, will return a solution if one exists –Otherwise will certify that no solution exists

8. Sequential Search CombinationalLogic Register Primary Inputs Primary Outputs Present State Previous State 1 Time Frame State Objectives State Solution

9. 3-Valued Search – DFS or BFS Obj 1 frame 0 S21S21 S11S11 S41S41 v20v20 S11S11 v10v10 v30v30 v40v40 frame 1 S52S52 S22S22 S12S12 v51v51 v21v21 v12v12 v11v11 frame 2 Initial State v23v23 v13v13 frame 3 Illegal State Legal State

10. State Cache internals State cubes are stored as state avoiding clauses State cubes are stored as state avoiding clauses State cube State cube –{s 0,s 1,..,s n } = {1,0,X,X,..,1} is stored as – (s 0 + s 1 + s n ) Imply new state cubes on the state cache Imply new state cubes on the state cache Conflicting cubes in the cache under the current assignments are covers Conflicting cubes in the cache under the current assignments are covers Smallest covers will conflict first Smallest covers will conflict first –Eg: Let new cube be {s 0,s 1,..,s n } = {1,0,1,X,..1,1} –We find implications of this assignment on state cache –Old cube (s 0 + s 1 + s n ) conflicts since it evaluates to FALSE

11. S ATORI – Assignment Reduction 0 0 0 0 1 0 1 1 1 0 0 G0 G6 G7 G1 G3 G5 G2 G13 G16 G15 G9 G11 G17 G10 G8 G14 G12 G14 G5’ G7’ G6’ State Variable Primary Input 1 1 0 1 G7 G0 G7 G0 G7 G0 G7 G0 G7 G0

12. Reachability Checking Set values of 0/1 on all lines in ISCAS’89 ckts Set values of 0/1 on all lines in ISCAS’89 ckts Check whether values are satisfiable from initial state Check whether values are satisfiable from initial state Compare with state-of-art commercial ATPG engine Compare with state-of-art commercial ATPG engine –No fault propagation –Even comparison

13. Effect of Path-Tracing

14. Assignment Reduction – State Cubes State Cube Comparisons

15. Reachability Checking

17. Safety property checking Sequential SAT in BFS mode does pre-image computation Sequential SAT in BFS mode does pre-image computation Check safety properties using pre-image computation Check safety properties using pre-image computation Test-cases drawn from VIS distribution Test-cases drawn from VIS distribution Sequential SAT uses a modified Buchi Automaton Sequential SAT uses a modified Buchi Automaton –Automaton goes to a Trap state when a counter- example is found –Automaton restricts search space to valid space for counter-examples –Effectively guides the search for a counter-example. Compare with VIS 2.0 (BDD based) Compare with VIS 2.0 (BDD based)

18. BDDs v/s SATORI – Pre-Image Computation

19. BDDs v/s SATORI – with Image Computation

20. Best Strategy Times: BDDs v/s SATORI

21. State space exploration Buggy states Initial states Witness vector trace Backward Search Forward Search

22. True Properties: VIS-BDDs v/s SATORI

23. False Properties: VIS-BDDs, BMC & SATORI

24. Performance on Selected false properties

25. In Summary Sequential SAT is complete Sequential SAT is complete One can do efficient reachability checking using sequential SAT One can do efficient reachability checking using sequential SAT –Competes with BDDs for property checking –Comparative performance is good Efficiency can be improved through improved search order Efficiency can be improved through improved search order