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ECE Synthesis & Verification 1 ECE 667 Synthesis and Verification of Digital Systems Formal Verification Combinational Equivalence Checking

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ECE Synthesis & Verification 2 Equivalence Checking Two circuits are functionally equivalent if they exhibit the same behavior Combinational circuits –for all possible input values In Out CL PoPI CL PsNs R Sequential circuits – for all possible input sequences

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ECE Synthesis & Verification 3 Application of EC in Microprocessor Designs Architectural Specification (informal) RTL Specification (Verilog, VHDL) Circuit Implementation (Gate level) Layout Implementation (GDS II) Cycle Simulation Equivalence Checking Circuit Simulation Test Programs

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ECE Synthesis & Verification 4 Application of EC in ASIC Designs RTL Specification Cell-Based Synthesis Standard Cell Implementation Engineering Changes (ECOs) Equivalence Checking Final Implementation Equivalence Checking

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ECE Synthesis & Verification 5 Combinational Equivalence Checking Functional Approach –transform output functions of combinational circuits into a unique (canonical) representation –two circuits are equivalent if their representations are identical –efficient canonical representation: BDD, BMD, etc. Structural –identify structurally similar internal points –prove internal points (cut-points) equivalent –find implications

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ECE Synthesis & Verification 6 Functional Equivalence Circuits for which BDD can be constructed –represent multi-output circuits as shared BDDs –BDDs must be identical (for the same variable ordering) Circuits whose BDDs are too large –cannot construct BDDs, memory problem –use partitioned BDD method decompose circuit into smaller pieces, each as BDD check equivalence of internal points (cut-point method)

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ECE Synthesis & Verification 7 EC Methods Structure- independent techniques Structural techniques Combined methods Degree of Structural Difference Size Structure-independent techniques: exhaustive simulation decision diagrams (*DD*) Structural techniques: graph hashing SAT solvers including learning techniques

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ECE Synthesis & Verification 8 Functional (structure-independent) Methods Decompose each function into functional blocks –represent each block as a BDD (partitioned BDD method) –define cut-points (z) –verify equivalence of blocks at cut-points starting at primary inputs F f2f2 f1f1 z x y G g2g2 g1g1 z x y

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ECE Synthesis & Verification 9 Cut-point based EC 0? f1f1 f2f2 f3f3 v1v1 v2v2 f1f1 f2f2 f3f3 v2v2 v1v1 x Cut-point guessing: Compute net signature with random simulator Sort signatures + select cut-points Iteratively verify and refine cut-points Verify outputs Cut-points are used to partition the Miter

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ECE Synthesis & Verification 10 Cut-Points Resolution Problem F f2f2 f1f1 z1z1 x y G g2g2 g1g1 z2z2 x y If all pairs of cut-points (z 1,z 2 ) are equivalent –so are the two functions, F,G If intermediate functions (f 2,g 2 ) are not equivalent –the functions (F,G) may still be equivalent –this is called false negative Why do we have false negative ? –functions are represented in terms of intermediate variables –to prove/disprove equivalence must represent the functions in terms of primary inputs (BDD composition)

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ECE Synthesis & Verification 11 Cut-Point Resolution – Theory Let f 1 (x)=g 1 (x) x –if f 2 (z,y) g 2 (z,y), z,y then f 2 (f 1 (x),y) g 2 (f 1 (x),y) F G –if f 2 (z,y) g 2 (z,y), z,y f 2 (f 1 (x),y) g 2 (f 1 (x),y) F G False negative –two functions are equivalent, but the verification algorithm declares them as different. F f2f2 f1f1 z x y G g2g2 g1g1 z x y We cannot say if F G or not

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ECE Synthesis & Verification 12 Cut-Point Resolution – cont’d Procedure 1: create a miter (XOR) between two potentially equivalent nodes/functions –perform ATPG test for stuck-at 0 –find test pattern to prove F G –efficient for true negative (gives test vector, a proof) –inefficient when there is no test 0, F G (false negative) 1, F G (true negative) FG How to verify if negative is false or true ?

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ECE Synthesis & Verification 13 Cut-Point Resolution – cont’d Procedure 2: create a BDD for F G –perform satisfiability analysis (SAT) of the BDD if BDD for F G = , problem is not satisfiable, false negative BDD for F G , problem is satisfiable, true negative Non-empty, F G , F G (false negative) F G = = F G Note: must compose BDDs until they are equivalent, or expressed in terms of primary inputs – the SAT solution, if exists, provides a test vector (proof of non-equivalence) – as in ATPG – unlike the ATPG technique, it is effective for false negative (the BDD is empty!)

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ECE Synthesis & Verification 14 Structural Equivalence Check Given two circuits, each with its own structure –identify “similar” internal points, cut sets –exploit internal equivalences False negative problem may arise –F G, but differ structurally (different local support) –verification algorithm declares F,G as different Solution: use BDD-based or ATPG-based methods to resolve the problem. Also: implication, learning techniques. b d1d1 a F a c d2d2 b G

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ECE Synthesis & Verification 15 Implication Techniques Techniques that extract and exploit internal correspondences to speed up verification Implications – direct and indirect a=1 c=x b=x f=0 d=0 e=0 a=0 c=x b=x f=1 d=x e=x Direct: a=1 f=0Indirect (learning): f=1 a=0

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ECE Synthesis & Verification 16 Learning Techniques Learning –process of deriving indirect implications –Recursive learning recursively analyzes effects of each justification –Functional learning uses BDDs to learn indirect implications 01 a b G 10 a b H G=1 H=0 a c b H G=1

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ECE Synthesis & Verification 17 Learning Techniques –cont’d Other methods to check implications G=1 H=0 –Build a BDD for G H’ If this function is satisfiable, the implication holds and gives a test vector Otherwise it does not hold –Since G=1 H=0 (G’+H’)=1, build a BDD for (G’+H’) The implication holds if (G’+H’)=1 (tautology) a c b H G=1

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ECE Synthesis & Verification 18 Summary Industrial EC checkers almost exclusively use a combinational EC paradigm –sequential EC is too complex, can only be applied to design with a few hundred state bits –combinational methods scale linearly with the design size for a given fixed size and “functional complexity” of the individual cones Still, pure BDDs and plain SAT solvers cannot handle all logic cones –BDDs can be built for about 80% of the cones of high-speed designs –less for complex ASICs –plain SAT blows up on a “Miter” structure Contemporary method highly exploit structural similarity of designs to be compared

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