Download presentation

Presentation is loading. Please wait.

Published bySerenity Life Modified over 2 years ago

1
Functional Test Generation using Constraint Logic Programming Zhihong Zeng, Maciej Ciesielski Dept. of Electrical & Comp. Engineering University of Massachusetts, Amherst Bruno Rouzeyre LIRMM, Université de Montpellier II

2
3-5 Dec. 2001VLSI-SOC 20012 Outline Introduction Functional test generation for design validation Related work on satisfiability (SAT) Boolean and hybrid approaches to SAT New word-level SAT solver Unified Boolean and arithmetic domains Based on Constraint Logic Programming Experimental results, conclusions

3
3-5 Dec. 2001VLSI-SOC 20013 Functional Simulation A viable approach to design validation Scales well with design size Predictable run time The way engineer thinks Downsides Incomplete, low “functional” coverage Confidence: when am I done? (coverage metrics are used to help)

4
3-5 Dec. 2001VLSI-SOC 20014 Functional Validation - typical scenario Coverage Normalized verification test cycles 50 % 80 % 100 % 100.0 1.0 Deterministic tests Pseudo-random directed tests Manual directed tests Test development time ?

5
3-5 Dec. 2001VLSI-SOC 20015 Deterministic Testing - Automation Functional test generation Given an RTL design and a coverage metric Goal: generate test vectors to reach predefined coverage goal Coverage metrics: code coverage, state coverage, transition coverage, etc Formulate as satisfiability (SAT) problem

6
3-5 Dec. 2001VLSI-SOC 20016 Our Design Validation Framework Simulation Seed Environment Symbolic Simulation (bounded time model) Symbolic Simulation (bounded time model) Convert to a SAT Problem Word-level SAT BDDs Boolean SAT BDDs Boolean SAT Next Simulation Target Done Y N

7
3-5 Dec. 2001VLSI-SOC 20017 Formulating a SAT Problem F s + D * A B C E 0 1 x Simulation target (value to be satisfied) state=s 3 F= b’0110 F> d’12 110011101110011101 Test vector Symbolic expression to be satisfied

8
3-5 Dec. 2001VLSI-SOC 20018 Design Validation of RTL Designs Behavioral or RT-level designs contain datapath and control logic Word-level arithmetic operators Boolean logic Previous approaches are not efficient Gate-level ATPG, Boolean SAT, BDDs – bit-level Word-level information is not utilized Need more abstract, word-level models

9
3-5 Dec. 2001VLSI-SOC 20019 Previous Work - Boolean SAT Based on Davis-Putnam procedure Tools: SATO, RelSat, GRASP, Chaff, … Conflict-based non-chronological back-jumping Conflict-based learning Variable ordering Restart Careful implementation BDD-based SAT WORD-LEVEL information is ignored!

10
3-5 Dec. 2001VLSI-SOC 200110 Previous Work - Hybrid SAT HSAT: [Fallah et al. DAC’98] CNF-based SAT to solve Boolean constraints Linear Programming relaxation to check consistency of arithmetic constraints ATPG + Arithmetic solver [Huang et al. DAC’00] Gate-level ATPG to justify objectives in Boolean domain Modular arithmetic solver to solve arithmetic constraints Word-level implications between two domains are attempted: weak, not robust

11
3-5 Dec. 2001VLSI-SOC 200111 Hybrid Approaches - Limitations Inefficient constraint propagation across domains: Boolean/arithmetic a=1 12>A A 3B+C B>C C>1 A<4C fghjfghj LKLK b f=1, g=1 h=1, j=1 k 1 Arithmetic solver: infeasible Conflict, backtrack 0 b

12
3-5 Dec. 2001VLSI-SOC 200112 Constraint Propagation – a Problem A better constraint propagation: tighter interaction between the two domains a=1 12>A A 3B+C B>C C>1 A<4C fghjfghj LKLK b 0 f=1, g=1 h=1, j=1 b Boolean to Arithmetic Arithmetic to Boolean A=11,C=2 k=0

13
3-5 Dec. 2001VLSI-SOC 200113 Our approach: Word-level SAT in a unified domain Put arithmetic and Boolean constraints in same domain Constraint propagation is implicit to one engine More efficient than hybrid approach Use the state-of-the-art constraint solving techniques No need to develop your own Branch & Bound procedure Constraint solving is extensively researched by AI, CS Our previous work LPSAT: SAT based on Linear Programming A new word-level SAT Based on constraint logic programming (CLP-SAT)

14
3-5 Dec. 2001VLSI-SOC 200114 Why Another Unified Approach? LPSAT [DATE’01]: SAT based on ILP Non-linear constraints must be linearized Numerical convergence problem (integers) Optimization engine CPLEX ($$, not a SAT solver) Alternative: SAT based on Constraint Logic Programming (CLP-SAT)

15
3-5 Dec. 2001VLSI-SOC 200115 CLP-SAT: SAT using Constraint Logic Programming Use Gnu-prolog as solving engine Publicly available Constraint solving over finite domain A native Prolog compiler: fast execution time Modeling is straightforward No need to linearize complex operators (MPY) Built-in predicates for Boolean gates

16
3-5 Dec. 2001VLSI-SOC 200116 Design/Constraint Modeling Identify Arithmetic and Boolean domains Word-level signals: B, D, E, X, Z (Partial) bit expansion: A, C, Y Y = Y[0] + 2*Y[1] + 4*Y[2] + … Single-bit Boolean signals: s A Z X Y < s + B D * C E 1 0

17
3-5 Dec. 2001VLSI-SOC 200117 CLP-SAT – Modeling the Constraints Arithmetic/BooleanGnu-Prolog Predicates Z = A * BZ #= A * B Z = and (A, B) A # B # Z Z = or (A, B) A # B # Z Z = not (A)A #\ Z Z = ite(s, A, B) (s #= 1) # (Z #= A), (s #= 0) # (Z #= B)

18
3-5 Dec. 2001VLSI-SOC 200118 Handling Modular Arithmetic A 16-bit adder: Z = A + B Z <= 2 8 + 16 8 A BZ ? D 9 Adding a free variable, D A+B = Z + D*2 8 D <= 2 9 Z <= 2 8 Z = (A+B) mod 256

19
3-5 Dec. 2001VLSI-SOC 200119 Handling Wide Arithmetic Operators > 56-bit s A B > 28-bit AHAH BHBH == 28-bit > 28-bit ALAL BLBL s Internal representation (computer): 32-bit words Largest domain in CLP is 28-bit Decompose using Boolean logic

20
3-5 Dec. 2001VLSI-SOC 200120 Experiments - Benchmarks M13 – 13-bit multipliers (sat, non) M16 – 16-bit multipliers, decomposed (sat, non) Square - compute Z 2 = X 2 + Y 2, 16-bit variables Quadratic - solve X 2 = a X + b for 16-bit X Linear-k- k-wide chain of comparators (k=40, 90), simple structure, large # inputs (over 1200) GCD-k- sequential circuit, 24-bit gcd unrolled k=20, 40 time frames Mdpe- multiplier feeding a dynamic priority encoder, taken from realistic design

21
3-5 Dec. 2001VLSI-SOC 200121 Benchmarks - Statistics BenchmarksCLP-SAT # lines LPSAT #constraints CNF-SAT #clauses M16x1611614924720 square52971077361 quadratic41346972015 Linear(2)3527274977887 gcd20876542117785 gcd4015151062248449 Mpde(2)685367330851

22
3-5 Dec. 2001VLSI-SOC 200122 Experimental Results Run-time speed-up TestcaseCLP-SATLPSATSATOGRASPCHAFF M16*16(s)3124.70.280.071 M16*16(n)214848.60--1 Square(1)520-- 0.231 Square(0)4135-- 1 Quadratic11020.480.351 Linear(1)0.83.20.240.401 Gcd201.1sec*0.03sec*-- Gcd401.9sec*0.08sec*-- Mdpe(1)12 0.180.021 *: real CPU time

23
3-5 Dec. 2001VLSI-SOC 200123 Conclusions Functional test generation for design validation Symbolic simulation + word-level SAT A new word-level SAT in a unified domain Based on constraint logic programming A good alternative to LPSAT Use the state-of-the-art constraint solving techniques Preliminary results are promising: Good for mixed arithmetic and Boolean logic Limitation: not competitive for designs with large portions of random logic

Similar presentations

OK

U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science Optimal Fixed-Size Controllers for Decentralized POMDPs Christopher Amato Daniel.

U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science Optimal Fixed-Size Controllers for Decentralized POMDPs Christopher Amato Daniel.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on holographic technology major Ppt on l&t finance share price Ppt on domain name system Pdf to ppt online tool Ppt on power system harmonics calculation Ppt on atrial septal defect Ppt on synthesis and degradation of purines and pyrimidines are what Ppt on chronic renal failure Ppt on unsustainable to sustainable development Ppt on chapter 3 atoms and molecules class