1. An Efficient Test Relaxation Technique for Synchronous Sequential Circuits Aiman El-Maleh and Khaled Al-Utaibi King Fahd University of Petroleum & Minerals Dhahran, Saudi Arabia {aimane, alutaibi}@ccse.kfupm.edu.sa

2. 2 Outline n Motivation n Problem Definition & Test Relaxation Techniques n Proposed Technique n Selection Criteria n Experimental Results n Conclusions

3. 3 Motivation n With today’s technology, complete systems with millions of transistors are built on a single chip. n Increasing complexity of systems-on-a-chip and its test data size increased cost of testing. n Cost of automatic test equipment increases with increase in speed, channel capacity, and memory. n Need for test data reduction is imperative Test compaction Test compression

4. 4 Motivation n Test compression and compaction techniques significantly improved based on a relaxed test. n Compression techniques: LFSR-Reseeding require the test vectors to be partially specified [Koenemann, ETS 91] [Hellebrand, ITS 92] Run-length coding benefits from partially specified test sets by specifying don't care values in a way that reduces number of runs [Jas, ITC 98] [Chandra, VTS 2000, VTS2001] [El-Maleh, VTS 2001, ICCD 2002] n Compaction: In overlapping techniques, increasing the number of X's in a test set reduces conflicts when merging two test sequences [Roy,88]

5. 5 Problem Definition & Test Relaxation Techniques n Given a synchronous sequential circuit and a fully specified test set, generate a partially specified test set that maintains the same fault coverage as the fully specified one while maximizing the number of unspecified bits. n Dynamic ATPG Compaction n Bitwise-Relaxation Test for every bit of the test set whether changing it to an X reduces the fault coverage or not. O(nm) fault simulation runs, where n is the width of one test vector, and m is the number of test vectors n Test Relaxation Techniques for Combinational circuits [El-Maleh, VTS 2002][Kajihara, ICCAD 2001]

6. 6 Proposed Test Relaxation Technique: General Behavior n At every time frame, t, all logic values necessary to detect a newly detected fault marked required. n Required logic values are justified backwards towards primary inputs and/or memory-elements. n Any primary input not marked as required during the justification process is relaxed. n Required values on the memory-elements are justified when time frame, t-1, is processed.

7. 7 Proposed Test Relaxation Technique: Relaxation Process n Fault Simulation: For every test vector t in the given test set, fault simulate the circuit under that test vector store faults newly detected in the current time frame store faults propagating to the next time frame n Backward Justification: Starting from the last time frame down to the first one, for every fault, f, that could not be justified in the previous time frame justify fault-free/faulty values necessary to propagate f for every fault f newly detected in the current frame justify fault-free/faulty values necessary to detect f

8. 8 Proposed Test Relaxation Technique: Example 0 1 x 0 /1/1/1/1 x 0 x 0 /1/1/1/1 1 /0/0/0/0 0 0 0 0 1 /0/0/0/0 n n Consider the circuit shown below under two test vectors: t i = 01 and t i+1 = 00. n n Assume that the only newly detected fault is A/1 n n Consider the circuit shown below under two test vectors: t i = 01 and t i+1 = 00. n n Assume that the only newly detected fault is A/1 A/1 /1/1/1/1

9. 9 Proposed Test Relaxation Technique: Example 0 /1/1/1/1 1/1 x/x 0 /1/1/1/1 x/x 0/0 x/x 0 /1/1/1/1 1 /0/0/0/0 0 /1/1/1/1 0/0 0/0 0/0 1 /0/0/0/0 n n Justify fault-free/faulty values necessary to detect A/1 starting from t i+1 A/1 x / 0 x / x

10. 10 Proposed Test Relaxation Technique: Example 0 /1/1/1/1 1/1 x/x 0 /1/1/1/1 x/x 0/0 x/x 0 /1/1/1/1 1 /0/0/0/0 x/x x/0 x/0 x/0 1 /0/0/0/0 n n Since G5 is a memory-element, its fault-free/fault value can not be justified in t i+1 n n Thus, the justification process will continue in t i n n Since G5 is a memory-element, its fault-free/fault value can not be justified in t i+1 n n Thus, the justification process will continue in t i x/1

11. 11 Selection Criteria in Value Justification n When justifying a controlling value through the inputs of a given gate, there could be more than one choice. n Priority is given to inputs already marked required n Otherwise, cost functions are used to guide the selection. n Cost functions give a relative measure on the number of primary inputs required to justify a given value.

12. 12 Selection Criteria n Let g be an AND Gate with i inputs and F(g) fanout branches [El-Maleh, VTS 2002] n Regular Cost Functions n Fanout-based Cost Functions n Weighted-Sum Cost Functions   i reg i C g C )()( 11  i i C g C )( min )( 00 )( )( )( 0 0 gF i C g C fan i  )( )( )( 1 1 gF i C g C i   )(.)(.)( )(.)(.)( 111 000 ggg ggg C B C A C C B C A C reg fanreg  

13. 13 Selection Criteria: Example C reg0 (A) = 1 C reg0 (B) = 1 C reg0 (C) = 1 C fan0 (A) = 1 C fan0 (B) = 0.5 C fan0 (C) = 1

14. 14 Selection Criteria: Sequential Circuits n Controllability values in one time frame depend on values in the current and previous frames. n Controllability values computed in an iterative manner starting from the first time frame. n Iterative computation of controllability over several time frames may cause regular cost function to grow much faster than fanout-based cost function. n Effect of the second cost function in the weighted sum may become negligible.

15. 15 Selection Criteria: Sequential Circuits

16. 16 Selection Criteria: Reconvergent Fanouts n The huge difference between the two costs is due to the reconverging fanout branches of the flip-flop. n Regular cost of a flip-flop with reconverging fanout branches should be adjusted to reduce the difference between the two costs n This can be done as follows. Let g be a flip-flop with n fanout branches. Assume that m out of the n fanout branches reconverge at some gate in the circuit, then The regular cost of every one of these branches equals to the regular cost of g divided by m.

17. 17 Selection Criteria: Reconvergent Fanouts C 1 = 1 C 1 = v C 1 = v/3 +1 C 1 = 2v/3 +1 C 1 = v+1 n n The three branches of stem B reconverge at gate G3 n n Thus, the regular cost of these branches will be divided by 3 n n The three branches of stem B reconverge at gate G3 n n Thus, the regular cost of these branches will be divided by 3

18. 18 Selection Criteria: Actual vs. General Values n Assuming general values on the gate inputs when computing the cost functions is less accurate than using the actual logical values. C 1 =3 C 1 =1 C 1 =2 C 1 =3

19. 19 Experimental Results n Experiments were performed on a number of ISCAS89 benchmarks. n Test sets generated by HITEC. n Comparison between proposed technique and bitwise-relaxation technique in terms of percentage of X’s and CPU time. n Experiments on Cost Functions.

20. 20 Proposed Tech. Vs Bitwise-Relaxation n The difference in the percentage of X’s ranges between 1% and 7%. n Average difference is about 3%.

21. 21 Proposed Tech. Vs Bitwise-Relaxation CPU Time (sec) CircuitNameProposedTechniqueBitwiseRelaxation S14231.750943 S14882.41712553 S14943.10013146 S32718.03387726 S33305.633115585 S33842.53316549 S48637.800162894 S537820.35218137

22. 22 Effect of cost functions on % of X’s CircuitNameA=0B=0A=0B=1A=1B=0A=1B=10A=1B=30A=1B=70A=1B=90 s142337.88250.86357.05962.43163.68664.03963.020 s148844.44872.45756.62466.21869.96871.57172.244 s149443.51572.66157.41066.68770.50272.09872.741 s327157.36178.86082.06082.01782.03381.89281.908 s333066.54885.25184.80585.44685.40785.50685.506 s338469.24771.70377.75577.79977.78477.75577.755 s486372.11478.93483.40682.84682.58282.03881.735 s537877.78885.69282.13084.11085.05385.09486.056 AVG58.61374.55372.65675.94477.12777.49977.621

23. 23 Conclusions n A new test relaxation technique for synchronous sequential circuits. n Proposed technique is faster than the bitwise- relaxation method by several order of magnitude. n Percentage of X’s obtained close to those obtained by bitwise-relaxation for most of the circuits. n Does not do any optimization in selecting POs for fault detection. This will be investigated in future work.