1. 1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 3/29/2006 Functional Blocks II and Simulation Design Manager: Abhishek Jajoo

2. 2Status  Project chosen: 16 bit Delta-Sigma ADC - Basic specs defined  Architecture  Schematic  Floor Planning  Revised Layout Dimensions  Layout Progress  Top Level Analog  Delta/Sigma Modulator  Low Pass Filter – DRC, LVS, Simulated  Top Level Digital  PII – DRC, LVS, Simulated  Sinc Filter – DRC, LVS, Simulated  Clock Divider – DRC, LVS, Simulated  Simulation / Verification  All Digital Modules Verified  All Analog Modules Verified  Overall/Top Verified  Optimized Layout  Analog Components  PII Function – Started Basic Optimization  Sinc Filter

3. 3 Analog Progress Delta/Sigma Modulator Delta/Sigma Modulator Transistor Level Verified with Behavioral Transistor Level Verified with Behavioral Layouts and Extracted Views of the Operational Amplifiers Layouts and Extracted Views of the Operational Amplifiers Integrator - Verified Integrator - Verified Comparator – Verified Comparator – Verified Completed DRC/LVS of Module Completed DRC/LVS of Module Common Centriod and MisMatch Analysis Common Centriod and MisMatch Analysis …Working on Analog Top Level Layout …Working on Analog Top Level Layout …Begin Schematic/Layout Verification …Begin Schematic/Layout Verification …Begin Optimizing Module Layout …Begin Optimizing Module Layout

4. 4 Delta/Sigma Modulator Transistor Level Simulation Wave Input Modulator Output

5. 5 Delta/Sigma Modulator Behavorial Level Simulation Wave Input Modulator Output

6. 6 ΔΣ Modulator Transistor - Layout 17 Analog Transistors Differential Op Amp Comparator

7. 7 Common Centroid (CC) Transistor Matching in Analog Design Transistor Matching in Analog Design Concept – Want matched pairs of transistors Concept – Want matched pairs of transistors (Voltage Matched) Differential Pairs (Voltage Matched) Differential Pairs (Current Matched) Current Mirrors (Current Matched) Current Mirrors Common Centroid Layout Common Centroid Layout Minimize effect of process gradients (ie etching) Minimize effect of process gradients (ie etching) Layout style with common center point Layout style with common center point Use of “fingers” method most common Use of “fingers” method most common Can be used for Matched Resistors/Capacitors Can be used for Matched Resistors/Capacitors

8. 8 Common Centroid Rules Coincidence : Centroids of matched devices should coincide Coincidence : Centroids of matched devices should coincide Symmetry : Symmetry should arise from the placement of segments in the array around both the X and Y-axes Symmetry : Symmetry should arise from the placement of segments in the array around both the X and Y-axes Dispersion : Segments of each device should be distributed throughout the array in a uniform manner Dispersion : Segments of each device should be distributed throughout the array in a uniform manner Compactness : Array should be as compact as possible and should be nearly square Compactness : Array should be as compact as possible and should be nearly square Orientation : Each matched device should consist of an equal number of segments oriented in either direction Orientation : Each matched device should consist of an equal number of segments oriented in either direction (Source: The Art of Analog Layout by Alan Hastings)

9. 9 Effects of Mismatch on ΔΣ Matched RC and Diff Pair Transistors Increased 10% Diff Pair Size Decreased 10% Diff Pair Size Only 10% RC Mismatch

10. 10 Comparator - Layout LR

11. 11 Sample CC Comparator - Layout R L L R

12. 12 Digital Progress Decimator Modules Decimator Modules PII Function - Transistor Level and Layout Verified & LVS PII Function - Transistor Level and Layout Verified & LVS Sinc Filter – Transistor Level and Layout Verified & LVS Sinc Filter – Transistor Level and Layout Verified & LVS Analysis - Power Consumption Analysis - Power Consumption Decimator Global Routing Decimator Global Routing Wired PII, Sinc Filter, and Clock Divider Wired PII, Sinc Filter, and Clock Divider LVS/DRC of the Decimator Layout LVS/DRC of the Decimator Layout …Decimator to be Simulated …Decimator to be Simulated …Some Optimization …Some Optimization Minimize Component (And/Or/Adder) Layouts Minimize Component (And/Or/Adder) Layouts Add additional contacts Add additional contacts Connect Nwells, Bigger-Better Vdd, Gnd Lines Connect Nwells, Bigger-Better Vdd, Gnd Lines Plan Vdd and Gnd Source Grids for Current Distribution Plan Vdd and Gnd Source Grids for Current Distribution Create Gnd Isolation Rings Create Gnd Isolation Rings …Continue to Optimize PII and Sinc …Continue to Optimize PII and Sinc

13. 13 Sinc Filter - Layout

14. 14 Sinc Filter Zoom - Layout

15. 15 Sinc (Schematic vs Layout) Schematic Simulation Layout Simulation

16. 16 PII Function - Layout

17. 17 PII Zoom - Layout

18. 18 PII (Schematic vs Layout) Schematic Simulation Layout Simulation

19. 19 Decimator – Layout Sinc2 Filter PII Function 256 Clock Divider

20. 20 Preliminary Top Level - Layout Min/Max/Out Wait Period Low Pass 1-Bit Stream

21. 21 Old Floorplan

22. 22 Updated Floorplan

23. 23 Layout Power/Timing ModulePowerAreaT-Count Clock Divider4.812uW1,740um^2334 2nd Order Sinc Filter227.1uW17,967um^23296 PII Function115.9uW17,955um^22782 Decimator (Top Digital)347.8uW (Estimate)45,474um^26412 Analog Op-Amps/Modulator ~162uW (Op Amp Power) --20 Low Pass FilterMax ~ 327.6uW59,899um^20 Modulator (Top Analog)Max ~ 837.4uW~137,764um^26,432

24. 24 Problems and Questions Isolation Rings Isolation Rings How Thick? How Thick? Around Analog Modulator? Around Analog Modulator? Around Decimator? Around Decimator? Current Distribution Issues? Current Distribution Issues? Any Comments or Suggestions? Any Comments or Suggestions?