1. 1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 4/10/2006 Let’s Go to the Dry Cleaners Design Manager: Abhishek Jajoo

2. 2Glitches

3. 3 Glitches (cont.)

4. 4Optimization VDD and GND Lines… VDD and GND Lines…

5. 5 Power Simulations Power simulations results jump up and down when evaluated before simulation completes Power simulations results jump up and down when evaluated before simulation completes Numbers range from nanowatts to milliwatts Numbers range from nanowatts to milliwatts Used standard equation for measuring power in Cadence Used standard equation for measuring power in Cadence abs(integ(VT(“/vdd!”)*IT(“/V0/PLUS”), 0, 1m))/1m abs(integ(VT(“/vdd!”)*IT(“/V0/PLUS”), 0, 1m))/1m Final results of simulation consistent and reasonable Final results of simulation consistent and reasonable Cadence possibly evaluating instantaneous power which is changing constantly Cadence possibly evaluating instantaneous power which is changing constantly Suggestion: don’t look at power simulation outputs until simulation is done! Suggestion: don’t look at power simulation outputs until simulation is done!

6. 6 Time of Simulations How to simulate entire design in Cadence at extractedRC level? How to simulate entire design in Cadence at extractedRC level? Simulation of just one clock tick (50 μs) of extractedRC of digital portion of design took about six hours Simulation of just one clock tick (50 μs) of extractedRC of digital portion of design took about six hours How to verify entire design before end of semester? How to verify entire design before end of semester?