1. Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 2/15/2006 Gate Level Design Design Manager: Abhishek Jajoo

2. Status  Design Proposal  Project chosen: 16 bit Delta-Sigma ADC  Basic specs defined  Architecture  Matlab Simulated  Behavioral Verilog - Simulated  Structural Verilog – Simulated  Schematic  Digital – All modules created, yet to be tested  Analog - More accurate model created  Floorplan  Revised floorplan  Layout  Intend to Bit Slice Sinc Filter and hopefully PII  Simulation / Verification

3. Algorithm Detail Decimation (Sinc Filter, Downsample) Measure Peak Amplitude (Peak Input Indicator) Digital Output Digital Peak Indicator Analog Input Lowpass Filter Analog to Digital Conversion (Delta-Sigma Modulator) Analog

4. Brief Analog Progress Decided upon RC values for Low Pass Filter Decided upon RC values for Low Pass Filter Decided Operational Amplifier Topologies Decided Operational Amplifier Topologies Modified Behavioral Schematic to more accurately model the desired real circuit. Modified Behavioral Schematic to more accurately model the desired real circuit. Tuned the modulator Tuned the modulator Will all be discussed in detail Next Week… Will all be discussed in detail Next Week…

5. Algorithm Detail Decimation (Sinc Filter, Downsample) Measure Peak Amplitude (Peak Input Indicator) Digital Output Digital Peak Indicator Analog Input Lowpass Filter Analog to Digital Conversion (Delta-Sigma Modulator) Digital

6. Digital Design Decisions Discovered governing formula for Digital Resolution from Brandt and Whooley. Discovered governing formula for Digital Resolution from Brandt and Whooley. 3 * log 2 (256) = Resolution 3 * log 2 (256) = Resolution Changed our design from 18 bits to 24 bits. Changed our design from 18 bits to 24 bits. Ran initial Schematic simulations. Ran initial Schematic simulations. Found glitches with clocking/timing. (Clk Divider) Found glitches with clocking/timing. (Clk Divider) Require buffering to correct. Require buffering to correct. Registered Y value coming out of the Sinc Filter as opposed using switching. Registered Y value coming out of the Sinc Filter as opposed using switching.

7. Digital Schematic – Decimator Overall

8. Hardware That Makes it Happen (Sinc Filter)

9. Schematic – Sinc Filter

10. Hardware That Makes it Happen (Peak Input Indicator)

11. Schematic - Peak Input Indicator

12. Hardware That Makes it Happen (Clock Divider)

13. Schematic - Clock Divider

14. Simulation – Overall Chip Now, we have simulated entire design in a mixed-signal environment Now, we have simulated entire design in a mixed-signal environment Analog portion represented by realistic behavioral components Analog portion represented by realistic behavioral components Digital portion represented by Structural Verilog code Digital portion represented by Structural Verilog code Simulated together in Cadence using AHDL Simulated together in Cadence using AHDL

15. Old Simulation – Overall Chip

16. New Simulation – Overall Chip

17. Digital Simulation Simulated behavioral and structural models of Decimator (Sinc Filter, PII function & Clock Divider) in ModelSim Simulated behavioral and structural models of Decimator (Sinc Filter, PII function & Clock Divider) in ModelSim Verified generation of Nyquist clock by clock divider module Verified generation of Nyquist clock by clock divider module Verified updates of maximum & minimum values of sinc filter output by PII function module Verified updates of maximum & minimum values of sinc filter output by PII function module

18. Digital Simulation Results

19. Revised Transistor Count Analog Analog 3 x Analog Op Amps, 3 x 24 = 72 3 x Analog Op Amps, 3 x 24 = 72 Resistive/Capacitive Elements Resistive/Capacitive Elements Digital Digital 8 x 24-bit registers, 8 x 530 = 4240 8 x 24-bit registers, 8 x 530 = 4240 1 x 12-bit register, 1 x 260 = 260 1 x 12-bit register, 1 x 260 = 260 8 x 24-bit adders, 8 x 680 = 5440 8 x 24-bit adders, 8 x 680 = 5440 1 x 24-bit counter, 1 x 870 = 870 1 x 24-bit counter, 1 x 870 = 870 1 x 7-bit counter, 1 x 250 = 250 1 x 7-bit counter, 1 x 250 = 250 1 x 12-bit equality function, 1 x 120 = 120 1 x 12-bit equality function, 1 x 120 = 120 2 x 24-bit muxes, 2 x 150 = 300 2 x 24-bit muxes, 2 x 150 = 300 Misc logic/Buffers = 500 Misc logic/Buffers = 500 Total = 11,980 transistors Total = 11,980 transistors Old Total = 9,300 Transistors Old Total = 9,300 Transistors

20. Initial Floorplan Total Area = 77, 750 sq μm

21. Revised Floorplan Total Area = 102,852 sq μm

22. Revised Power Consumption We’ll be using 1.8V source We’ll be using 1.8V source Estimate chip’s total power ~3 mW Estimate chip’s total power ~3 mW Digital Portion –.256 uW Digital Portion –.256 uW P = C * V 2 * f P = C * V 2 * f Power = 5 MHz * (1.8 V) 2 * 3.16 pF Power = 5 MHz * (1.8 V) 2 * 3.16 pF Capacitance Estimated from previous projects (based on 322) Capacitance Estimated from previous projects (based on 322) Analog Portion – 2.5 mW Analog Portion – 2.5 mW P = IV P = IV 3 Op Amps * (150uA * 1.8 V) = 2.5 mW 3 Op Amps * (150uA * 1.8 V) = 2.5 mW

23. Problems and Questions Even More Transistors Even More Transistors ~12,000 transistors is a lot for 3 digital designers ~12,000 transistors is a lot for 3 digital designers A lot of repetition A lot of repetition Can always reduce design (PII function, clock divider) Can always reduce design (PII function, clock divider) Analog RC Components Analog RC Components Keep them on chip? Keep them on chip? Outsource the analog low pass filter due to size constraints. Outsource the analog low pass filter due to size constraints.

24. Results More comfortable with overall design More comfortable with overall design Gate level Design Completed Gate level Design Completed Structural Verilog simulations Structural Verilog simulations Overall schematic including both analog & digital portions of design Overall schematic including both analog & digital portions of design Topology, RLC selection for analog parts (next week) Topology, RLC selection for analog parts (next week) Coming up Next: Coming up Next: Schematic Simulation Schematic Simulation Layout Layout Gate Sizing - Analog Gate Sizing - Analog