1. Reticle Floorplanning With Guaranteed Yield for Multi-Project Wafers Andrew B. Kahng ECE and CSE Dept. University of California San Diego Sherief Reda CSE Dept. University of California San Diego

2. Outline  Introduction to Multi-Project Wafers  Design Flow  Side-to-Side Dicing Problem  Proposed Methodology: Floorplanning with Guaranteed Yield  Experimental Results

3. Mask and Wafer Cost  Mask cost: $1M for 90 nm technology  Wafer cost: $4K per wafer

4. Introduction to Multi-Project Wafer  Share rising costs of mask tooling among multiple prototype and low production volume designs → Multi-Project Wafer Image courtesy of CMP and EuroPractice

5. History of Multi-Project Wafer  Introduced in late 1970s and early 1980s  Companies: MOSIS, CMP, TSMC  Several academic approaches proposed: 1.Chen et al. give bottom-left fill algorithm, SPIE 2003 2.Xu, Tian, Wong and Reich, SPIE 2003 3.Anderson et al. propose a grid packing algorithm, WADS 2003 4.Kahng et al. propose dicing plans for generic floorplans, ISPD 2004  Commercial Tools: MaskCompose, GTMuch

6. Outline Introduction to Multi-Project Wafers  Design Flow  Side-to-Side Dicing Problem  Proposed Methodology: Floorplanning with Guaranteed Yield  Experimental Results

7. Design Flow  Unique designs

8. Design Flow  Custom designs  Partition between reticles

9. Design Flow  Custom designs  Partition between shuttles  Reticle placement

10. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map print shot-map

11. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design

12. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design

13. Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design  Extract die

14. Outline Introduction to Multi-Project Wafers Design Flow  Side-to-Side Dicing Problem  Proposed Methodology: Floorplanning with Guaranteed Yield  Experimental Results

15. Why is Dicing a Problem? Sliced out  A die is sliced out if and only if: 1. Four edges are on the cut lines 2. No cut lines pass through the die Dicing is easy for standard wafers. All dice will be sliced out. Dicing is complex for MPW. Most dice will be destroyed if placement is not well aligned.  Side-to-side dicing is the prevalent wafer dicing technology

16. Die Conflict  Two dies are in conflict if they can not be simultaneously sliced out horizontally.  Die 1 is in conflict with entire row of Die 2. 1 2 43 1 2 43 1 2 43 1 2 43

17. Dicing Plan 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 11 2 3 4 66 66 5 2 3 4 dicing die 2 dicing die 1 wafer reticle die  A die copy is successfully extracted if it is successfully extracted in both horizontal and vertical dicing

18. MPW Floorplanning Objectives Produce the required volumes of all dies using the minimum amount of wafers → maximize the minimium amount of die copies extracted from a wafer over all dies (Yield) Objective: Given: A number of die designs, each with a production volume requirement Example: If die 1 has a 40 copies requirement, and the dicing plan yields 5 valid copies per wafer → 8 wafers are needed Methods: 1.Floorplanning the dies within the reticle 2.Efficient dicing plan

19. Outline Introduction to Multi-Project Wafers Design Flow Side-to-Side Dicing Problem and Motivation  Proposed Methodology: Floorplanning with Guaranteed Yield  Experimental Results

20. Motivation  Previous approaches (Kahng et al.) use regular area floorplanning and devise efficient dicing plans  Regular area floorplanners are yield oblivious  There is an inherent conflict between area minimization and yield Observation: 11 2 3 4 66 66 5 2 3 4

21. Proposed Approach  Construct floorplans that consider specified yield bounds as constraints and minimize the area 1.Limit floorplans to grids 2.Calculate constructive lower bounds on the yield 3.Specify simple rules to characterize the yield of a given floorplan 4.Minimize the area using a branch and bround procedure taking the yield as a constraint Main Idea: Method:

22. 1. Grid Floorplans 11 2 3 4 66 66 5 2 3 4 11 2 3 4 6 6 6 6 5 2 3 4 General floorplanGrid floorplan

23. 2. Constructive Yield Lower Bounds reticle row reticle column 11 2 3 4 6 6 6 6 5 2 3 4 grid row grid column  Given m reticle rows and n reticle columns  Let γ i be the number of different height die copies residing in a grid row, e.g., γ 1 =2, γ 1 =1  Let μ j be the number of different width die copies residing in a grid column, e.g., μ 1 =1, μ 2 =2 Lemma 1: A constructive lower bound on number of copies that can be extracted of a die residing in row i and column j is  m / γ i    n / μ j  n m

24. 3. Rules for Yield Specification reticle row reticle column 11 2 3 4 6 6 6 6 5 2 3 4 grid row grid column  Limiting the values of μ j and γ i guarantees a lower limit on yield  γ i : number of different height die copies residing in a grid row.  μ j : be the number of different width die copies residing in a grid column μjμj γiγi γiμjγiμj Yield 111100 12250 212 31330 22425 Example Theorem 1: A lower bound on the yield is m 2 -m(γ i  μ j )/γ i  μ j for a wafer with m rows and m columns

25. 4. Branch and Bound Area Packer Why is branch and bound feasible? 1. There are typically few dies per reticle 2. Yield constraints prune large portions of the search space branch_bound(k, yield, grid[1..w][1..h]) if all dies are placed then evaluate the floorplan area and if area < best area then area = best area return expand the grid by an additional column and row: grid[1..w+1][1..h+1] for each empty slot (i, j) in the grid: if placing die d k in slot (i, j) does not violate yield constraints: Place d k and evaluate partial area if partial area < best area then branch_bound(k+1, yield, grid[1..w+1][1..h+1]) undo placement of d k in (i, j)

26. Outline Introduction to Multi-Project Wafers Design Flow Side-to-Side Dicing Problem and Motivation Proposed Methodology: Floorplanning with Guaranteed Yield  Experimental Results

27. Experimental Results: Yield/Area results Test Case # Die Die area Yield 10050302520 110231494312288270264 218226396286275260275 311252456312300290288 49203500300264252256 510226560336285260280 615227494306275276275 715234416297280270280 814232416297280270273 910231494312288270264 1020215360270240270240 Total227745863028277526882443  Our method allows an area/yield trade off

28. Experimental Results: Comparison against Previous Work Test Case # Die Die area GTMuchPrevious App. (kahng et al.) Our Approach YieldAreaYieldAreaCPUYieldAreaCPU 110231182552828880302880.02 2182261628525270783282604705 3112521528030294132302900.15 492031822130288118302640.01 510226122722526094252600.03 6152271028518238226302756.41 7152341428520285782252701.46 8142322028520288152252701.55 9102312028528288161302880.01 1020215630420260102030240278.0 Total227714927572442757354828327055088  Our results dominate previous approaches in both yield and area

29. Experimental Results: Pareto Frontier  Our results establish a Pareto frontier representing a trade off between area and yield

30. Conclusions and Future Work  A new simple approach to reticle floorplanning taking yield as a constraint  An optimal area packer using branch and bound  Our results establish a Pareto frontier that trades yield for area  Our results dominate previous approaches  Respecting reticle aspect ratios  Different dicing plans for different wafers Conclusions Future Work

31. Thank you for your attention!