Presentation is loading. Please wait.

Presentation is loading. Please wait.

Minimum Implant Area-Aware Gate Sizing and Placement Andrew B. Kahng and Hyein Lee UC San Diego VLSI CAD Laboratory.

Similar presentations


Presentation on theme: "Minimum Implant Area-Aware Gate Sizing and Placement Andrew B. Kahng and Hyein Lee UC San Diego VLSI CAD Laboratory."— Presentation transcript:

1 Minimum Implant Area-Aware Gate Sizing and Placement Andrew B. Kahng and Hyein Lee UC San Diego VLSI CAD Laboratory

2 2 Minimum Implant Area Constraint Motivation Prior Work Minimum Implant Area-Aware Placement and Sizing Experimental Results Conclusions and Future Work Outline

3 3 Implant (active) layers Regions for ion implantation (= V t ) Same as the entire cell region in most cases Limitation of optical lithography (at λ=193nm) Cannot make small patterns Minimum implant area constraint ⇒ A small island of implant layer is not allowed ⇒ Challenge for physical design in sub-22nm nodes Minimum Implant Area (MinIA) Constraint H H L L L L Minimum implant width constraint Violation Implant area for P, NMOS

4 4 MUST consider neighbor cells’ size and Vt type New physical design problems: placement and sizing Motivation: MinIA Constraint in Sub-22nm Nodes H H MinIA constraint WAS: OK In previous nodes L L L L Minimum cell size > MinIA constraint NOW: Violation In sub-22nm nodes L L L L H H Minimum cell size < MinIA constraint

5 5 Traditional placement and sizing are separate problems Placement problem: Place each cell without overlap Gate sizing problem: Select size and Vt of each cell to minimize power under timing/design constraints MinIA-aware placement and sizing ⇒ No longer independent of each other in sub-22nm nodes Sizing needs to understand placement Example: Changing Vt can create MinIA violations depending on the placement Placement, sizing and MinIA constraints MUST be considered together Motivation: MinIA-Aware Placement and Sizing L L L L L L H H L L L L

6 6 Redefine the traditional placement and gate sizing problems to capture new placement, sizing and MinIA rule interaction Propose placement and sizing heuristics to optimize power under the MinIA constraint Our proposed methods are implemented in C++ and incorporated into a standard P&R flow Our placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violations Our sizing and placement heuristic achieves comparable power reduction to the conventional sizing approach without creating MinIA violations Our Work

7 7 Gate sizing, and co-optimization with placement Method to minimize power and ECO cost Sequential optimization of placement and sizing Linear (1-D) placement Graph model-based approach Dynamic programming Layout effect-aware placement STI stress-aware placement No work considers the MinIA rules in placement and/or sizing Prior Work: Literature

8 8 Case study of P&R tools Technology: 45nm technology with modified MinIA rules Commercial P&R tools fix MinIA violations by inserting filler cells Result of two commercial tools Commercial tools cannot fix all of MinIA violations Prior Work: Commercial P&R Tools 50% remaining violations

9 9 Minimum Implant Area Constraint Motivation Prior Work Minimum Implant Area-Aware Placement and Sizing Experimental Results Conclusions and Future Work Outline

10 10 Problem: MinIA-aware sizing and placement Minimize power Subject to: Minimum implant area constraints Timing constraints (slack, transition time) No overlap in placement Sizing and placement are performed sequentially Problem Formulation

11 11 We perform sizing and placement sequentially in our optimization Three combinations of sizing and placement problems Free sizing and MinIA-aware placement Allow MinIA violations and fix the violations later Strict MinIA-aware sizing Do not allow any MinIA violations during sizing Relaxed MinIA-aware sizing and MinIA-aware placement Allow fixable MinIA violations Used for our optimizer Sequential Optimization

12 12 Levers to solve MinIA violations How to Fix MinIA Violations? H H L L L L H H L L L L H H L L L L L L L L L L H H L L L L Violation We must make the blue area larger than MinIA constraint (dashed red box)

13 13 Our Heuristic Flow: Placement Insert same V t filler cells around violating cells V t swap the violating cell/ its neighbor cells to match V t Calculate whitespace for violating cells Move neighbor cells to obtain spacing Insert filler cells Downsize neighbor cells to obtain spacing #Vio = 0? N finish #Vio = 0? N Y finish #Vio = 0? N Y finish Insert filler cells finish Y timing check is needed

14 14 Our Heuristic Flow: Sizing and Placement Add the cell to the candidate list Calculate sensitivity Pick the most promising cell And commit Fix MinIA violations Fixable? Y discard Timing feasible? N Y N Revert Sensitivity function = ∆leakage/∆TNS TNS = total negative slack ∆TNS is calculated considering sizing and MinIA costs

15 15 Our Optimizer P&R Design (DEF)/LEF MinIA-Aware Placement/Sizing min implant layer rules geometry info def/lef2oa Timer Tool/ P&R Tool (DB update, ECO sizing/ placement/ routing) MinIA Violation Check Tcl socket OADB Final P&R Design Timing update Apply solutions save P&R Design MinIAOpt

16 16 Minimum Implant Area Constraint Motivation Prior Work Minimum Implant Area-Aware Placement and Sizing Experimental Results Conclusions and Future Work Outline

17 17 Technology: 45nm technology with modified MinIA rules Testcases dma, mpeg, aes and jpeg from OpenCore High utilization (75~82%) is used Many small cells are used (% of minimum size cells : 59~84%) Additional testcases (aes_var*) with different V t cell distributions Various minimum implant width constraints Experimental Setup Testcase#inst.Orig. #Vio. dma mpeg aes jpeg aes_var aes_var aes_var Const.Min. width (# sites)% of violating lib. cells (in a lib.) Const143% Const2612% Const3728%

18 18 How much MinIA violations can be fixed by our placement heuristic? Placement results with Const3 Our approach fixes almost all of violations while commercial tools cannot fix up to 64% of violations Experimental Results: Placement 64% vs. 3%

19 19 Which sizing heuristics show good results w.r.t. both power reduction and MinIA constraints? Comparison results between the three heuristics Our sizing heuristic (3) does not increase MinIA violations while maintaining low leakage power Experimental Results: Sizing and Placement F (1) Best leakage reduction (1) Many MinIA violations (2) Some MinIA violations (2) Worst leakage reduction (3) Small MinIA violations (3) Good leakage reduction

20 20 We address new gate sizing and placement problems arising in sub-22nm VLSI due to MinIA constraint We propose a heuristic sizing and placement method considering MinIA Our placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violations Our sizing and placement heuristic achieves comparable power reduction without creating MinIA violations Conclusion

21 21 Single-row placement with MinIA fixing by using dynamic programming Unified placement, sizing and Vt-swap heuristics Multi-row placement consideration Future Work MinIA violations H H L L L L H H L L L L H H Standard cell row1 Standard cell row2

22 22 THANK YOU!


Download ppt "Minimum Implant Area-Aware Gate Sizing and Placement Andrew B. Kahng and Hyein Lee UC San Diego VLSI CAD Laboratory."

Similar presentations


Ads by Google