Presentation on theme: "Minimum Implant Area-Aware Gate Sizing and Placement"— Presentation transcript:
1Minimum Implant Area-Aware Gate Sizing and Placement Andrew B. Kahng and Hyein LeeUC San Diego VLSI CAD LaboratoryThank you for the kind introduction. Good morning everyone. The title of this talk is “Minimum Implant Area-Aware Gate Sizing and Placement”.
2Outline Minimum Implant Area Constraint Motivation Prior Work Minimum Implant Area-Aware Placement and SizingExperimental ResultsConclusions and Future WorkIn this talk, I will first explain the “minimum implant area constraint” and the motivation of this work.Then, the prior work and the study on existing P&R tools will be presented.Next, I will explain our minimum implant area-aware placement and sizing method.Finally, I will present experimental results and give the conclusion with future work discussion.
3Minimum Implant Area (MinIA) Constraint Implant (active) layersRegions for ion implantation (= Vt)Same as the entire cell region in most casesLimitation of optical lithography (at λ=193nm)Cannot make small patternsMinimum implant area constraint⇒ A small island of implant layer is not allowed⇒ Challenge for physical design in sub-22nm nodes<Standard cell layout>Implant area for P, NMOSHLMinimum implant width constraintViolationIn the semiconductor process, it is not easy to generate small patterns due to limitation of the current optical lithography technology.So, such small patterns are prohibited by design rules like minimum area or width constraints.This give us a big challenge for physical implementation in sub-22nm nodes, since the feature sizes are small.The design rules are applied to implant layers as well.Implant layers define the region for ion implantation which determines threshold voltage of a cell.The implant layer covers the entire region of a standard cell in most cases.Minimum implant area constraint does not allow a small island of a certain implant layer.
4Motivation: MinIA Constraint in Sub-22nm Nodes MUST consider neighbor cells’ size and Vt typeNew physical design problems: placement and sizingHMinIA constraintWAS: OKIn previous nodesLMinimum cell size> MinIA constraintNOW: ViolationIn sub-22nm nodesLHMinimum cell size< MinIA constraintThe minimum implant area rule, or MinIA had existed in previous nodes.But, it was not a big problem because the minimum cell size was larger than the MinIA constraint.So, we don’t need to consider interaction between cells.On the other hand, in sub-22nm nodes, the minimum size cell is smaller than the MinIA constraint.In this case, depending on which cells are adjacent, some placement may not be legal with respect to MinIA constraint.So, we need to check neighbor cells’ size and Vt type when performing sizing and placement, to not create the violations.This means that the traditional placement and sizing problems are not as simple as previous anymore.
5Motivation: MinIA-Aware Placement and Sizing Traditional placement and sizing are separate problemsPlacement problem: Place each cell without overlapGate sizing problem: Select size and Vt of each cell to minimize power under timing/design constraintsMinIA-aware placement and sizing ⇒ No longer independent of each other in sub-22nm nodesSizing needs to understand placementExample: Changing Vt can create MinIA violations depending on the placementPlacement, sizing and MinIA constraints MUST be considered togetherLHTraditional placement and sizing problems are totally independent each other.Placement problem is to place all standard cells within a chip boundary, without any overlap.Traditional gate sizing problem is to select a proper size and vt option for each cell, such that the power is minimized under timing and other design constraints.However, when it comes to MinIA constraints, these two problems are no longer independent.In other words, sizing needs to understand placement.Without considering placement and neighbor cells, sizing can create MinIA violations.For example, if the vt type of a small cell is changed, it can create MinIA violation if the cell is sandwiched between different vt layers.So, we need to consider placement, sizing and MinIA constraints together, since they cannot be separated.
6Our WorkRedefine the traditional placement and gate sizing problems to capture new placement, sizing and MinIA rule interactionPropose placement and sizing heuristics to optimize power under the MinIA constraintOur proposed methods are implemented in C++ and incorporated into a standard P&R flowOur placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violationsOur sizing and placement heuristic achieves comparable power reduction to the conventional sizing approach without creating MinIA violationsIn this work, we redefine the traditional placement and gate sizing problem considering the MinIA constraint.The new problem captures the interaction between placement, sizing and the minIA rule.And we propose few placement legalization approaches to fix MinIA violations.Based on our approaches, we propose placement and sizing heuristics to optimize power under MinIA constraint.Our proposed methods are implemented with C++ and incorporated into a standard P&R flow.
7Prior Work: Literature Gate sizing, and co-optimization with placementMethod to minimize power and ECO costSequential optimization of placement and sizingLinear (1-D) placementGraph model-based approachDynamic programmingLayout effect-aware placementSTI stress-aware placementNo work considers the MinIA rules in placement and/or sizingCo-optimization of gate sizing and placement has been studied in few literatures.One work proposes a method to minimize power and ECO cost at the same time.Another work suggests sequential placement and sizing optimization.Since we consider the MinIA constraint within a row, row-based placement approaches are related.There are several papers that propose graph model-based approach and dynamic programming-based approach.About layout effect-aware placement, STI stress-aware placement is suggested.However, no work has addressed MinIA problem in placement and sizing problem.
8Prior Work: Commercial P&R Tools Case study of P&R toolsTechnology: 45nm technology with modified MinIA rulesCommercial P&R tools fix MinIA violations by inserting filler cellsResult of two commercial toolsCommercial tools cannot fix all of MinIA violations50% remaining violationsWe also studied commercial tools’ capability of fixing MinIA violations.Commercial tools have been supporting MinIA-aware physical implementation.Commercial tools fix MinIA violations by inserting filler cells.We test how well the commercial tools fix the MinIA violations.This chart shows the % of remaining MinIA violations after applying the recommended flow from the tools’ user guides.As a result, we have found that commercial P&R tools cannot fix all of violations. At worst case, 50% of violations remain.
9Outline Minimum Implant Area Constraint Motivation Prior Work Minimum Implant Area-Aware Placement and SizingExperimental ResultsConclusions and Future WorkFrom now, I will present our minimum implant area-aware placement and sizing.
10Problem: MinIA-aware sizing and placement Problem FormulationProblem: MinIA-aware sizing and placementMinimize powerSubject to:Minimum implant area constraintsTiming constraints (slack, transition time)No overlap in placementSizing and placement are performed sequentiallyThe goal of MinIA-aware sizing and placement problem is to minimize power with legal placementsubject to timing constraints,minimum implant area constraints.Also, the placement result should not have overlaps.We define a MinIA-aware placement as a subproblem.The goal is to minimize the MinIa violations subject to timing constraint.In this work, we perform sizing and placement sequentially.In the next slide, I will explain how we combine the two problems.
11Sequential Optimization We perform sizing and placement sequentially in our optimizationThree combinations of sizing and placement problemsFree sizing and MinIA-aware placementAllow MinIA violations and fix the violations laterStrict MinIA-aware sizingDo not allow any MinIA violations during sizingRelaxed MinIA-aware sizing and MinIA-aware placementAllow fixable MinIA violationsUsed for our optimizerIn our optimization, we perform sizing and placement sequentially.We combine sizing and placement problems in three ways.First, size cells freely as the conventional method and fix all MinIA violations at placement stage.This method can achieve minimum power, since less constrained, but might increase MinIA violations.Second, restrict sizing to avoid MinIA violations. It may not achieve maximum power reduction.Third, the combination of MinIA-aware sizing and MinIA-aware placement.I will show the results of each method later.
12How to Fix MinIA Violations? Levers to solve MinIA violationsViolationWe must make the blue area larger than MinIA constraint (dashed red box)HLHLHLThis slide shows how we solve the MinIA violations.Suppose that we have MinIA violation for HVT layer in the between two LVT layers as shown in this figure.We must make this blue HVT area larger than the MinIA constraint, which is indicated by the dashed red box.We can try moving neighbor cells to get some space around the HVT layer. Then, we can insert HVT filler cells to make the HVT layer wider.Similarly, to get spaces around the HVT, neighbor cells can be downsized and we can insert filler cells again.Also, we can change the HVT layer to LVT so that we do not have the island of HVT layer.Note that timing check is needed after all these changes.<Move neighbor cells><Downsize neighbor cells>HLL<Change Vt of cells>
13Our Heuristic Flow: Placement timing check is neededCalculate whitespacefor violating cellsMove neighbor cellsto obtain spacingInsert same Vt filler cellsaround violating cellsInsert filler cellsfinish#Vio = 0?#Vio = 0?finishYYNNVt swap the violating cell/its neighbor cellsto match VtThis slide shows our placement heuristic flow.By using the levers presented in the previous slide, we fix MinIA violations one by one.For each violation, we first calculate whitespacae for violating cells, so that we insert filler cells to fix the violation.If the violation is not fixed, then we try Vt swap if it does not violate timing.If the violation cannot be fixed after that, we try moving and downsizing neighbor cells to get space for filler cell insertion.The order of these steps is decided based on our experiment results.For each step, timing is always checked so as to ensure no timing violation.Downsize neighbor cellsto obtain spacingInsert filler cells#Vio = 0?finishYNfinish
14Our Heuristic Flow: Sizing and Placement Calculate sensitivitySensitivity function =∆leakage/∆TNSTNS = total negative slack∆TNS is calculated considering sizing and MinIA costsFixable?discardNYAdd the cellto the candidate listPick the most promising cellAnd commitThis slide shows our sizing heuristic flow.We use sensitivity-based gate sizing.The sensitivity function is calculated based on the impact of gate sizing on power and timing.When calculating sensitivity function, we consider potential timing overhead from MinIA violation fix.If the candidate gate sizing solution creates MinIA violation that is not fixable, we discard it.After all sensitivity calculations, the most promising cell is picked and committed.Then, we fix MinIA violations if needed.If the design is not timing feasible, we revert the change.Fix MinIA violationsRevertTiming feasible?YN
15Our Optimizer P&R Design (DEF)/LEF min implant layer rules geometry infoMinIAOptdef/lef2oaTimer Tool/P&R Tool(DB update,ECO sizing/placement/routing)OADBMinIA Violation CheckTcl socketMinIA-AwarePlacement/SizingApply solutionsThis slide shows our optimizer.The input files include DEF and LEF, which have geometry information and minimum implant layer rules.We use OpenAccess API to support standard DEF/LEF format.In our C++ program, we check MinIA violations first, and perform MinIA-aware placement and sizing.We use commercial timer and P&R tool to apply our solution and check timing.For efficiency, we use a Tcl socket interface to communicate with the commercial tools.Once we apply our solutions, we perform ECO routing with P&R tool to get accurate timing information.Timing updatesave P&R DesignFinal P&R Design
16Outline Minimum Implant Area Constraint Motivation Prior Work Minimum Implant Area-Aware Placement and SizingExperimental ResultsConclusions and Future WorkNow, I will present the experimental results and conclude my talk with future work discussion.
17% of violating lib. cells (in a lib.) Experimental SetupTechnology: 45nm technology with modified MinIA rulesTestcasesdma, mpeg, aes and jpeg from OpenCoreHigh utilization (75~82%) is usedMany small cells are used (% of minimum size cells : 59~84%)Additional testcases (aes_var*) with different Vt cell distributionsVarious minimum implant width constraintsTestcase#inst.Orig. #Vio.dma1168193mpeg7121693aes96111146jpeg449117864aes_var12955aes_var22558aes_var31816We use 45nm technology with modified MinIA rules so that we can project MinIA violations in future nodes.For testcases, we use four testcaes from opencore, which are implemented with high utilization and many small cells.We implement several variations of aes testcase, by tweaking Vt cell distribution to create more MinIA violations.The table on the right side shows the statics of testcases.The second column shows the number of instances, and the third column shows the number of MinIA violations in the initial designs.For MinIA rules, we define three constraints as shown in this table.The minimum width are four, six and seven for const1, 2 and 3 respectively.Const1 is the most relaxed and const3 is the tightest rule.The third column shows the portion of library cells that are are smaller than the MinIA constraint.Const.Min. width (# sites)% of violating lib. cells (in a lib.)Const143%Const2612%Const3728%
18Experimental Results: Placement How much MinIA violations can be fixed by our placement heuristic?Placement results with Const3Our approach fixes almost all of violations while commercial tools cannot fix up to 64% of violations64% vs. 3%This slide shows the placement result for const3, which is the tightest MinIA rule.The y-axis represents the % of remaining MinIA violations after applying each solution.The blue bars show the results of a commercial tool, and the red bars show our results.As you can see in this chart, our approach fixes most of violations.Especially, for aes_var1, only 3% MinIA violations remain after applying our flow,while 64% MinIA violations cannot be fixed by the commercial tool.
19Experimental Results: Sizing and Placement Which sizing heuristics show good results w.r.t. both power reduction and MinIA constraints?Comparison results between the three heuristicsOur sizing heuristic (3) does not increase MinIA violations while maintaining low leakage powerF(1) Many MinIA violations(1) Best leakage reduction(2) Some MinIA violations(2) Worst leakage reduction(3) Small MinIA violations(3) Good leakage reductionThis slide shows the comparison results between three heuristics that I presented before.The blue bars show the results of the free sizing, the red bars show the results of strict sizing, and the green bars show MinIA-aware sizing.The left chart shows the % of the delta MinIA violations after applying the solutions, and the right chart shows the leakage reduction resultThe conventional sizing shows the best result in terms of power reduction, but it creates many MinIA violations as shown in the left chart.The strict sizing shows less leakage reduction but smaller MinIA violations are created compared to the conventional sizing.We observed that the additional MinIA violations come from neighbor cells, since strict MinIA-aware sizing does not consider secondary effect of the sizing.The relaxed MinIA-aware sizing shows comparable leakage reduction to conventional sizing with minimum MinIA violations.From the result, we see that our third sizing heuristic shows the smallest increase in the number of MinIA violations while maintaining low leakage power.
20ConclusionWe address new gate sizing and placement problems arising in sub-22nm VLSI due to MinIA constraintWe propose a heuristic sizing and placement method considering MinIAOur placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violationsOur sizing and placement heuristic achieves comparable power reduction without creating MinIA violationsIn this talk, we address the new gate sizing and placement problem considering the minimum implant area constraints, which becomes a big issue in sub-22nm nodes.We propose a heuristic sizing and placement method considering MinIA.Our method fixes most of MinIA violations while a commercial tool cannot fix up to 64% of violations.Also, we show that our sizing + placement heuristic achieves comparable power reduction without creating MinIA violations.
21Future WorkSingle-row placement with MinIA fixing by using dynamic programmingUnified placement, sizing and Vt-swap heuristicsMulti-row placement considerationMinIA violationsHLStandard cell row1Standard cell row2For the future work, we want to study single-row placement by using dynamic programming to develop an algorithm to obtain optimal solutions.Also, we want to unify our placement and sizing heuristics.Lastly, in this work, we do not consider multi-row placement. We recently observe that MinIA violation can exist across rows as shown in this figure. For the future study, we want to consider the interaction across standard cell rows.