1. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Performed by: Dabran Shalev, Papir Eran Instructor: Orbach Mony Spring 2005 CRC –GENERATOR (Cyclic Redundancy Check)

2. Agenda Goals Goals Current working system Current working system The new system The new system CRC Generator and Analyzer CRC Generator and Analyzer Packet structure Packet structure What is CRC? What is CRC? Schedule Schedule

3. Project goals: Developing a 16bit CRC-GENRATOR for the Rocket I/O experiment using to the VirtexII-pro

4. Current System Virtex II-pro PPC To PC Packet Generation Patterns PLB Test Status Storage Traffic Generator Traffic Analyzer Rocket I/O Transceiver BRAM 1 BRAM 2

5. Virtex II-pro PPC To PC Packet Generation Patterns PLB Test Status Storage Traffic Generator Traffic Analyzer Rocket I/O Transceiver BRAM 1 BRAM 2 CRC Generator CRC Analyzer The new system

6. CRC generator Input : a stream of double word data Input : a stream of double word data Output: the same data + 16 bit CRC Output: the same data + 16 bit CRC

7. CRC Analyzer Input : a stream of double word data +16 bit CRC Input : a stream of double word data +16 bit CRC Output: the accepted data and error check Output: the accepted data and error check

8. Packet structure HeaderStamp End Current system HeaderStamp End New system CRC

9. What is CRC? M(x) = Our DATA G(x) = The chosen polynomial n = degree of G(x)

10. Schedule 4-6 weeks – CRC hardware implementation 4-6 weeks – CRC hardware implementation 3-5 weeks - integration 3-5 weeks - integration 3 weeks – Tests 3 weeks – Tests 4 weeks – documentation 4 weeks – documentation

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