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10/25/2007 ITC-07 Paper 26.31 Delay Fault Simulation with Bounded Gate Delay Model Soumitra Bose Design Technology, Intel Corp. Folsom, CA 95630 Hillary.

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Presentation on theme: "10/25/2007 ITC-07 Paper 26.31 Delay Fault Simulation with Bounded Gate Delay Model Soumitra Bose Design Technology, Intel Corp. Folsom, CA 95630 Hillary."— Presentation transcript:

1 10/25/2007 ITC-07 Paper 26.31 Delay Fault Simulation with Bounded Gate Delay Model Soumitra Bose Design Technology, Intel Corp. Folsom, CA 95630 Hillary Grimes and Vishwani D. Agrawal Dept. of ECE, Auburn University Auburn, AL 36849

2 10/25/2007 ITC-07 Paper 26.32 Purpose Investigate min-max delay simulation used for process variation Improve upon existing min-max delay simulation  Determination of f max (VTS’07)  Determination of delay fault detection (this paper)

3 10/25/2007 ITC-07 Paper 26.33 Outline Background  Min-max Delay Simulation  Determination of f max  Hazard Lists Fault Detection  Correcting the detection threshold Finding f max vs Fault Detection Results

4 10/25/2007 ITC-07 Paper 26.34 Definitions Guaranteed failure frequency (f max )  This is the lowest clock frequency above which all (even the fastest) circuits will fail. Testing at f max will show a failure if a delay fault, detectable by the vectors, exists (Bose et al., 1993). Gate delay fault  Assume that a delay fault is lumped at a faulty gate (Pramanick & Reddy, ITC’88)  All other gates have their delays within the specified (min, max) range.

5 10/25/2007 ITC-07 Paper 26.35 Min-Max Delay Simulation 1,3 1,2 3,4 1 3 2 5 3 5 5 9 4 11 1/f max 0 1 1

6 10/25/2007 ITC-07 Paper 26.36 Reconvergent Fanout Analysis 1,3 1,2 3,4 1 x 3 3 5 5 9 4 6 11 Fall occurs at time ‘x’ x+1 5 Output rises at least 1 unit after ‘x’ Hazard cannot occur 0 1 1

7 10/25/2007 ITC-07 Paper 26.37 Determination of f max 1,3 1,2 3,4 3 5 5 9 4 6 11 1 3 2 5 1/f max 0 1 1

8 10/25/2007 ITC-07 Paper 26.38 Hazard Lists Hazard Lists generated at fanout points contains  originating fanout name  ambiguity interval Propagate hazard lists through downcone of fault site  similar to fault lists in concurrent fault simulation

9 10/25/2007 ITC-07 Paper 26.39 Hazard List Propagation Hazard lists at the inputs of a reconvergent gate help determine its output  If signal correlations are such that no hazard can occur, the hazard is suppressed  Otherwise, the hazard lists are propagated to the gate’s output, and ambiguity intervals are updated

10 10/25/2007 ITC-07 Paper 26.310 Fault Detection We want to make sure the fault is detected Propagating hazard lists allows signal correlations to be used More accurate fault detection and detection threshold calculations

11 10/25/2007 ITC-07 Paper 26.311 Detection Threshold 1,3 1,2 3,4 1 3 2 5 3 5 5 9 4 11 T c = 12 Threshold = 8 0 1 1

12 10/25/2007 ITC-07 Paper 26.312 Corrected Detection Threshold 1,3 1,2 3,4 3 5 5 9 4 6 11 1 3 2 5 T c = 12 Threshold = 6 0 1 1

13 10/25/2007 ITC-07 Paper 26.313 Finding f max vs Fault Detection A circuit output may have multiple ambiguity regions 4 6 7 10 3 4 4,6 3,4 0 0

14 10/25/2007 ITC-07 Paper 26.314 Finding f max Determination of f max finds the leading transition of the last ambiguity region that occurs 4 6 7 10 3 4 4,6 3,4 0 0 1/f max

15 10/25/2007 ITC-07 Paper 26.315 Fault Detection Fault detection finds the minimum delay that would shift the last ambiguity region to guarantee detection 4 6 7 10 3 4 4,6 3,4 0 0 T c = 11

16 10/25/2007 ITC-07 Paper 26.316 Fault Detection A faulty inverter with delay size 4 or greater is guaranteed to be detected 4 6 7 10 3 4 4,6 3,4 0 0 T c = 11

17 10/25/2007 ITC-07 Paper 26.317 Fault Detection A faulty AND gate with size between 4 and 5 is guaranteed to be detected. 4 6 7 10 3 4 4,6 3,4 0 0 T c = 11

18 10/25/2007 ITC-07 Paper 26.318 Fault Detection 4,5 1,4 0 0 X 0,0 4,6 2,2 4 6 7 8 11 T c =12 3 4 4 5 1 4 3 6

19 10/25/2007 ITC-07 Paper 26.319 Results Circuit Number of Gate Faults Coverage % Critical Gate Delay Faults Bounded Delay Fault Simulation (BDFS) % Iyengar et al. BDFS with Hazard Suppression % (this paper) c43242097.142.6 c135595298.735.615.6 c2670189098.935.926.1 c5315349670.716.78.1 c7552766699.212.09.0 Column 2: The number of gate delay faults - Both slow-to-rise & slow-to-fall transitions

20 10/25/2007 ITC-07 Paper 26.320 Results Circuit Number of Gate Faults Coverage % Critical Gate Delay Faults Bounded Delay Fault Simulation (BDFS) % Iyengar et al BDFS with Hazard Suppression % (this paper) c43242097.142.6 c135595298.735.615.6 c2670189098.935.926.1 c5315349670.716.78.1 c7552766699.212.09.0 Column 3: Fault coverage achieved – detection assumed irrespective of fault size. Equivalent to transition fault coverage.

21 10/25/2007 ITC-07 Paper 26.321 Results Circuit Number of Gate Faults Coverage % Critical Gate Delay Faults Bounded Delay Fault Simulation (BDFS) % Iyengar et al BDFS with Hazard Suppression % (this paper) c43242097.142.6 c135595298.735.615.6 c2670189098.935.926.1 c5315349670.716.78.1 c7552766699.212.09.0 Columns 4 & 5: Consider only detected faults that lie on paths with length at least 70% of the longest path; detectable delay fault size below 30% of critical path delay.

22 10/25/2007 ITC-07 Paper 26.322 Results Circuit Number of Gate Faults Coverage % Critical Gate Delay Faults Bounded Delay Fault Simulation (BDFS) % Iyengar et al BDFS with Hazard Suppression % (this paper) c43242097.142.6 c135595298.735.615.6 c2670189098.935.926.1 c5315349670.716.78.1 c7552766699.212.09.0 Columns 4 & 5: About ½ critical gate delay faults can be erroneously assumed to be detected if signal reconvergences are ignored.

23 10/25/2007 ITC-07 Paper 26.323 Conclusion Conventional min-max delay simulation produces extra hazards because correlations between signals are neglected. Future work: General analysis of reconvergent fanouts  How does this analysis affect static timing analysis?  Timing simulation?  Dynamic timing analysis?

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